LTEWatch 1.0
Master Thesis - LTE-M/NB-IoT & GNSS - Smart-Watch Application
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Macros
devicetree_unfixed.h File Reference

Go to the source code of this file.

Macros

#define DT_N_PATH   "/"
 
#define DT_N_FULL_NAME   "/"
 
#define DT_N_FOREACH_CHILD(fn)   fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_cryptocell_sw) fn(DT_N_S_leds) fn(DT_N_S_buttons) fn(DT_N_S_reserved_memory) fn(DT_N_S_zephyr_user)
 
#define DT_N_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cryptocell_sw, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__)
 
#define DT_N_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_cryptocell_sw) fn(DT_N_S_leds) fn(DT_N_S_buttons) fn(DT_N_S_reserved_memory) fn(DT_N_S_zephyr_user)
 
#define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cryptocell_sw, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__)
 
#define DT_N_ORD   0
 
#define DT_N_REQUIRES_ORDS   /* nothing */
 
#define DT_N_SUPPORTS_ORDS
 
#define DT_N_EXISTS   1
 
#define DT_N_INST_0_nordic_ltewatch_nrf9160   DT_N
 
#define DT_N_REG_NUM   0
 
#define DT_N_RANGES_NUM   0
 
#define DT_N_FOREACH_RANGE(fn)
 
#define DT_N_IRQ_NUM   0
 
#define DT_N_COMPAT_MATCHES_nordic_ltewatch_nrf9160   1
 
#define DT_N_STATUS_okay   1
 
#define DT_N_PINCTRL_NUM   0
 
#define DT_N_P_compatible   {"nordic,ltewatch_nrf9160"}
 
#define DT_N_P_compatible_IDX_0   "nordic,ltewatch_nrf9160"
 
#define DT_N_P_compatible_IDX_0_TOKEN   nordic_ltewatch_nrf9160
 
#define DT_N_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_LTEWATCH_NRF9160
 
#define DT_N_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N, compatible, 0)
 
#define DT_N_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N, compatible, 0, __VA_ARGS__)
 
#define DT_N_P_compatible_LEN   1
 
#define DT_N_P_compatible_EXISTS   1
 
#define DT_N_S_aliases_PATH   "/aliases"
 
#define DT_N_S_aliases_FULL_NAME   "aliases"
 
#define DT_N_S_aliases_PARENT   DT_N
 
#define DT_N_S_aliases_CHILD_IDX   1
 
#define DT_N_S_aliases_FOREACH_CHILD(fn)
 
#define DT_N_S_aliases_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_aliases_ORD   1
 
#define DT_N_S_aliases_REQUIRES_ORDS    0, /* / */
 
#define DT_N_S_aliases_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_aliases_EXISTS   1
 
#define DT_N_S_aliases_REG_NUM   0
 
#define DT_N_S_aliases_RANGES_NUM   0
 
#define DT_N_S_aliases_FOREACH_RANGE(fn)
 
#define DT_N_S_aliases_IRQ_NUM   0
 
#define DT_N_S_aliases_STATUS_okay   1
 
#define DT_N_S_aliases_PINCTRL_NUM   0
 
#define DT_N_S_chosen_PATH   "/chosen"
 
#define DT_N_S_chosen_FULL_NAME   "chosen"
 
#define DT_N_S_chosen_PARENT   DT_N
 
#define DT_N_S_chosen_CHILD_IDX   0
 
#define DT_N_S_chosen_FOREACH_CHILD(fn)
 
#define DT_N_S_chosen_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_chosen_ORD   2
 
#define DT_N_S_chosen_REQUIRES_ORDS    0, /* / */
 
#define DT_N_S_chosen_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_chosen_EXISTS   1
 
#define DT_N_S_chosen_REG_NUM   0
 
#define DT_N_S_chosen_RANGES_NUM   0
 
#define DT_N_S_chosen_FOREACH_RANGE(fn)
 
#define DT_N_S_chosen_IRQ_NUM   0
 
#define DT_N_S_chosen_STATUS_okay   1
 
#define DT_N_S_chosen_PINCTRL_NUM   0
 
#define DT_N_S_cryptocell_sw_PATH   "/cryptocell-sw"
 
#define DT_N_S_cryptocell_sw_FULL_NAME   "cryptocell-sw"
 
#define DT_N_S_cryptocell_sw_PARENT   DT_N
 
#define DT_N_S_cryptocell_sw_CHILD_IDX   6
 
#define DT_N_S_cryptocell_sw_FOREACH_CHILD(fn)
 
#define DT_N_S_cryptocell_sw_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_cryptocell_sw_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_cryptocell_sw_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_cryptocell_sw_ORD   3
 
#define DT_N_S_cryptocell_sw_REQUIRES_ORDS    0, /* / */
 
#define DT_N_S_cryptocell_sw_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_cryptocell_sw_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_cc310_sw   DT_N_S_cryptocell_sw
 
#define DT_N_NODELABEL_cryptocell_sw   DT_N_S_cryptocell_sw
 
#define DT_N_S_cryptocell_sw_REG_NUM   0
 
#define DT_N_S_cryptocell_sw_RANGES_NUM   0
 
#define DT_N_S_cryptocell_sw_FOREACH_RANGE(fn)
 
#define DT_N_S_cryptocell_sw_IRQ_NUM   0
 
#define DT_N_S_cryptocell_sw_COMPAT_MATCHES_nordic_nrf_cc310_sw   1
 
#define DT_N_S_cryptocell_sw_STATUS_okay   1
 
#define DT_N_S_cryptocell_sw_PINCTRL_NUM   0
 
#define DT_N_S_cryptocell_sw_P_label   "CRYPTOCELL_SW"
 
#define DT_N_S_cryptocell_sw_P_label_STRING_TOKEN   CRYPTOCELL_SW
 
#define DT_N_S_cryptocell_sw_P_label_STRING_UPPER_TOKEN   CRYPTOCELL_SW
 
#define DT_N_S_cryptocell_sw_P_label_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_cryptocell_sw_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_cryptocell_sw_P_label_EXISTS   1
 
#define DT_N_S_cryptocell_sw_P_status   "okay"
 
#define DT_N_S_cryptocell_sw_P_status_STRING_TOKEN   okay
 
#define DT_N_S_cryptocell_sw_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_cryptocell_sw_P_status_ENUM_IDX   1
 
#define DT_N_S_cryptocell_sw_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_cryptocell_sw_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_cryptocell_sw_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_cryptocell_sw_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_cryptocell_sw_P_status_EXISTS   1
 
#define DT_N_S_cryptocell_sw_P_compatible   {"nordic,nrf-cc310-sw"}
 
#define DT_N_S_cryptocell_sw_P_compatible_IDX_0   "nordic,nrf-cc310-sw"
 
#define DT_N_S_cryptocell_sw_P_compatible_IDX_0_TOKEN   nordic_nrf_cc310_sw
 
#define DT_N_S_cryptocell_sw_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_CC310_SW
 
#define DT_N_S_cryptocell_sw_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_cryptocell_sw_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_cryptocell_sw, compatible, 0)
 
#define DT_N_S_cryptocell_sw_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_cryptocell_sw, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_cryptocell_sw_P_compatible_LEN   1
 
#define DT_N_S_cryptocell_sw_P_compatible_EXISTS   1
 
#define DT_N_S_cryptocell_sw_P_wakeup_source   0
 
#define DT_N_S_cryptocell_sw_P_wakeup_source_EXISTS   1
 
#define DT_N_S_entropy_bt_hci_PATH   "/entropy_bt_hci"
 
#define DT_N_S_entropy_bt_hci_FULL_NAME   "entropy_bt_hci"
 
#define DT_N_S_entropy_bt_hci_PARENT   DT_N
 
#define DT_N_S_entropy_bt_hci_CHILD_IDX   4
 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD(fn)
 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_entropy_bt_hci_ORD   4
 
#define DT_N_S_entropy_bt_hci_REQUIRES_ORDS    0, /* / */
 
#define DT_N_S_entropy_bt_hci_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_entropy_bt_hci_EXISTS   1
 
#define DT_N_INST_0_zephyr_bt_hci_entropy   DT_N_S_entropy_bt_hci
 
#define DT_N_NODELABEL_rng_hci   DT_N_S_entropy_bt_hci
 
#define DT_N_S_entropy_bt_hci_REG_NUM   0
 
#define DT_N_S_entropy_bt_hci_RANGES_NUM   0
 
#define DT_N_S_entropy_bt_hci_FOREACH_RANGE(fn)
 
#define DT_N_S_entropy_bt_hci_IRQ_NUM   0
 
#define DT_N_S_entropy_bt_hci_COMPAT_MATCHES_zephyr_bt_hci_entropy   1
 
#define DT_N_S_entropy_bt_hci_STATUS_okay   1
 
#define DT_N_S_entropy_bt_hci_PINCTRL_NUM   0
 
#define DT_N_S_entropy_bt_hci_P_status   "okay"
 
#define DT_N_S_entropy_bt_hci_P_status_STRING_TOKEN   okay
 
#define DT_N_S_entropy_bt_hci_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_entropy_bt_hci_P_status_ENUM_IDX   1
 
#define DT_N_S_entropy_bt_hci_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_entropy_bt_hci_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_entropy_bt_hci_P_status_EXISTS   1
 
#define DT_N_S_entropy_bt_hci_P_compatible   {"zephyr,bt-hci-entropy"}
 
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0   "zephyr,bt-hci-entropy"
 
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_TOKEN   zephyr_bt_hci_entropy
 
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_UPPER_TOKEN   ZEPHYR_BT_HCI_ENTROPY
 
#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_entropy_bt_hci, compatible, 0)
 
#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_entropy_bt_hci_P_compatible_LEN   1
 
#define DT_N_S_entropy_bt_hci_P_compatible_EXISTS   1
 
#define DT_N_S_entropy_bt_hci_P_wakeup_source   0
 
#define DT_N_S_entropy_bt_hci_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_PATH   "/soc"
 
#define DT_N_S_soc_FULL_NAME   "soc"
 
#define DT_N_S_soc_PARENT   DT_N
 
#define DT_N_S_soc_CHILD_IDX   2
 
#define DT_N_S_soc_FOREACH_CHILD(fn)   fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_40000000) fn(DT_N_S_soc_S_gpiote_40031000)
 
#define DT_N_S_soc_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_40031000, __VA_ARGS__)
 
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_40000000) fn(DT_N_S_soc_S_gpiote_40031000)
 
#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_40031000, __VA_ARGS__)
 
#define DT_N_S_soc_ORD   5
 
#define DT_N_S_soc_REQUIRES_ORDS    0, /* / */
 
#define DT_N_S_soc_SUPPORTS_ORDS
 
#define DT_N_S_soc_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf9160_sica   DT_N_S_soc
 
#define DT_N_INST_0_nordic_nrf9160   DT_N_S_soc
 
#define DT_N_INST_0_nordic_nrf91   DT_N_S_soc
 
#define DT_N_INST_0_simple_bus   DT_N_S_soc
 
#define DT_N_S_soc_REG_NUM   0
 
#define DT_N_S_soc_RANGES_NUM   0
 
#define DT_N_S_soc_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_IRQ_NUM   0
 
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf9160_sica   1
 
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf9160   1
 
#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf91   1
 
#define DT_N_S_soc_COMPAT_MATCHES_simple_bus   1
 
#define DT_N_S_soc_STATUS_okay   1
 
#define DT_N_S_soc_PINCTRL_NUM   0
 
#define DT_N_S_soc_P_compatible   {"nordic,nRF9160-SICA", "nordic,nRF9160", "nordic,nRF91", "simple-bus"}
 
#define DT_N_S_soc_P_compatible_IDX_0   "nordic,nRF9160-SICA"
 
#define DT_N_S_soc_P_compatible_IDX_0_TOKEN   nordic_nRF9160_SICA
 
#define DT_N_S_soc_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF9160_SICA
 
#define DT_N_S_soc_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_P_compatible_IDX_1   "nordic,nRF9160"
 
#define DT_N_S_soc_P_compatible_IDX_1_TOKEN   nordic_nRF9160
 
#define DT_N_S_soc_P_compatible_IDX_1_UPPER_TOKEN   NORDIC_NRF9160
 
#define DT_N_S_soc_P_compatible_IDX_1_EXISTS   1
 
#define DT_N_S_soc_P_compatible_IDX_2   "nordic,nRF91"
 
#define DT_N_S_soc_P_compatible_IDX_2_TOKEN   nordic_nRF91
 
#define DT_N_S_soc_P_compatible_IDX_2_UPPER_TOKEN   NORDIC_NRF91
 
#define DT_N_S_soc_P_compatible_IDX_2_EXISTS   1
 
#define DT_N_S_soc_P_compatible_IDX_3   "simple-bus"
 
#define DT_N_S_soc_P_compatible_IDX_3_TOKEN   simple_bus
 
#define DT_N_S_soc_P_compatible_IDX_3_UPPER_TOKEN   SIMPLE_BUS
 
#define DT_N_S_soc_P_compatible_IDX_3_EXISTS   1
 
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_P_compatible_LEN   4
 
#define DT_N_S_soc_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_PATH   "/soc/interrupt-controller@e000e100"
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME   "interrupt-controller@e000e100"
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_PARENT   DT_N_S_soc
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_IDX   0
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_ORD   6
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_REQUIRES_ORDS    5, /* /soc */
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_SUPPORTS_ORDS
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS   1
 
#define DT_N_INST_0_arm_v8m_nvic   DT_N_S_soc_S_interrupt_controller_e000e100
 
#define DT_N_NODELABEL_nvic   DT_N_S_soc_S_interrupt_controller_e000e100
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_NUM   1
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS   3758153984 /* 0xe000e100 */
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE   3072 /* 0xc00 */
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_RANGES_NUM   0
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_NUM   0
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MATCHES_arm_v8m_nvic   1
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_STATUS_okay   1
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg   {3758153984 /* 0xe000e100 */, 3072 /* 0xc00 */}
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0   3758153984
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1   3072
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits   3
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS   1
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller   1
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS   1
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible   {"arm,v8m-nvic"}
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0   "arm,v8m-nvic"
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_TOKEN   arm_v8m_nvic
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_UPPER_TOKEN   ARM_V8M_NVIC
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0)
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_LEN   1
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source   0
 
#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_PATH   "/soc/peripheral@40000000"
 
#define DT_N_S_soc_S_peripheral_40000000_FULL_NAME   "peripheral@40000000"
 
#define DT_N_S_soc_S_peripheral_40000000_PARENT   DT_N_S_soc
 
#define DT_N_S_soc_S_peripheral_40000000_CHILD_IDX   3
 
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000) fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000)
 
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000) fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000)
 
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_ORD   7
 
#define DT_N_S_soc_S_peripheral_40000000_REQUIRES_ORDS    5, /* /soc */
 
#define DT_N_S_soc_S_peripheral_40000000_SUPPORTS_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_REG_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_RANGES_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS   0 /* 0x0 */
 
#define DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS   1073741824 /* 0x40000000 */
 
#define DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_VAL_LENGTH   268435456 /* 0x10000000 */
 
#define DT_N_S_soc_S_peripheral_40000000_FOREACH_RANGE(fn)   fn(DT_N_S_soc_S_peripheral_40000000, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_PATH   "/soc/peripheral@40000000/adc@e000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FULL_NAME   "adc@e000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_CHILD_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_CHILD(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_ORD   8
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_SUPPORTS_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_saadc   DT_N_S_soc_S_peripheral_40000000_S_adc_e000
 
#define DT_N_NODELABEL_adc   DT_N_S_soc_S_peripheral_40000000_S_adc_e000
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_IDX_0_VAL_ADDRESS   1073799168 /* 0x4000e000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_irq   14
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_COMPAT_MATCHES_nordic_nrf_saadc   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg   {57344 /* 0xe000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_0   57344
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts   {14 /* 0xe */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_0   14
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible   {"nordic,nrf-saadc"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_IDX_0   "nordic,nrf-saadc"
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_IDX_0_TOKEN   nordic_nrf_saadc
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_SAADC
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_PATH   "/soc/peripheral@40000000/gpio@842500"
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FULL_NAME   "gpio@842500"
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_CHILD_IDX   31
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_ORD   9
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REQUIRES_ORDS    7, /* /soc/peripheral@40000000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_SUPPORTS_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_gpio   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_NODELABEL_gpio0   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_IDX_0_VAL_ADDRESS   1082402048 /* 0x40842500 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_IDX_0_VAL_SIZE   768 /* 0x300 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_COMPAT_MATCHES_nordic_nrf_gpio   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg   {8660224 /* 0x842500 */, 768 /* 0x300 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_0   8660224
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_1   768
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_port   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_port_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_gpio_controller   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_gpio_controller_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_ngpios   32
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_ngpios_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible   {"nordic,nrf-gpio"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_IDX_0   "nordic,nrf-gpio"
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_IDX_0_TOKEN   nordic_nrf_gpio
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_GPIO
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_wakeup_source_EXISTS   1
 
#define DT_N_S_zephyr_user_PATH   "/zephyr,user"
 
#define DT_N_S_zephyr_user_FULL_NAME   "zephyr,user"
 
#define DT_N_S_zephyr_user_PARENT   DT_N
 
#define DT_N_S_zephyr_user_CHILD_IDX   10
 
#define DT_N_S_zephyr_user_FOREACH_CHILD(fn)
 
#define DT_N_S_zephyr_user_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_zephyr_user_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_zephyr_user_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_zephyr_user_ORD   10
 
#define DT_N_S_zephyr_user_REQUIRES_ORDS
 
#define DT_N_S_zephyr_user_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_zephyr_user_EXISTS   1
 
#define DT_N_S_zephyr_user_REG_NUM   0
 
#define DT_N_S_zephyr_user_RANGES_NUM   0
 
#define DT_N_S_zephyr_user_FOREACH_RANGE(fn)
 
#define DT_N_S_zephyr_user_IRQ_NUM   0
 
#define DT_N_S_zephyr_user_STATUS_okay   1
 
#define DT_N_S_zephyr_user_PINCTRL_NUM   0
 
#define DT_N_S_zephyr_user_P_io_channels_IDX_0_EXISTS   1
 
#define DT_N_S_zephyr_user_P_io_channels_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_adc_e000
 
#define DT_N_S_zephyr_user_P_io_channels_IDX_0_VAL_input   3
 
#define DT_N_S_zephyr_user_P_io_channels_IDX_0_VAL_input_EXISTS   1
 
#define DT_N_S_zephyr_user_P_io_channels_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_zephyr_user, io_channels, 0)
 
#define DT_N_S_zephyr_user_P_io_channels_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_zephyr_user, io_channels, 0, __VA_ARGS__)
 
#define DT_N_S_zephyr_user_P_io_channels_LEN   1
 
#define DT_N_S_zephyr_user_P_io_channels_EXISTS   1
 
#define DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_VAL_pin   27
 
#define DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_VAL_flags   0
 
#define DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_zephyr_user_P_disp_en_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_zephyr_user, disp_en_gpios, 0)
 
#define DT_N_S_zephyr_user_P_disp_en_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_zephyr_user, disp_en_gpios, 0, __VA_ARGS__)
 
#define DT_N_S_zephyr_user_P_disp_en_gpios_LEN   1
 
#define DT_N_S_zephyr_user_P_disp_en_gpios_EXISTS   1
 
#define DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_VAL_pin   12
 
#define DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_VAL_flags   0
 
#define DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_zephyr_user_P_bat_lvl_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_zephyr_user, bat_lvl_gpios, 0)
 
#define DT_N_S_zephyr_user_P_bat_lvl_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_zephyr_user, bat_lvl_gpios, 0, __VA_ARGS__)
 
#define DT_N_S_zephyr_user_P_bat_lvl_gpios_LEN   1
 
#define DT_N_S_zephyr_user_P_bat_lvl_gpios_EXISTS   1
 
#define DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_VAL_pin   11
 
#define DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_VAL_flags   0
 
#define DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_zephyr_user_P_batlvl_en_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_zephyr_user, batlvl_en_gpios, 0)
 
#define DT_N_S_zephyr_user_P_batlvl_en_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_zephyr_user, batlvl_en_gpios, 0, __VA_ARGS__)
 
#define DT_N_S_zephyr_user_P_batlvl_en_gpios_LEN   1
 
#define DT_N_S_zephyr_user_P_batlvl_en_gpios_EXISTS   1
 
#define DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_VAL_pin   10
 
#define DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_VAL_flags   1
 
#define DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_zephyr_user_P_batchrg_int_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_zephyr_user, batchrg_int_gpios, 0)
 
#define DT_N_S_zephyr_user_P_batchrg_int_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_zephyr_user, batchrg_int_gpios, 0, __VA_ARGS__)
 
#define DT_N_S_zephyr_user_P_batchrg_int_gpios_LEN   1
 
#define DT_N_S_zephyr_user_P_batchrg_int_gpios_EXISTS   1
 
#define DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_VAL_pin   25
 
#define DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_VAL_flags   1
 
#define DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_zephyr_user_P_gps_rst_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_zephyr_user, gps_rst_gpios, 0)
 
#define DT_N_S_zephyr_user_P_gps_rst_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_zephyr_user, gps_rst_gpios, 0, __VA_ARGS__)
 
#define DT_N_S_zephyr_user_P_gps_rst_gpios_LEN   1
 
#define DT_N_S_zephyr_user_P_gps_rst_gpios_EXISTS   1
 
#define DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_VAL_pin   26
 
#define DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_VAL_flags   0
 
#define DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_zephyr_user_P_gps_en_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_zephyr_user, gps_en_gpios, 0)
 
#define DT_N_S_zephyr_user_P_gps_en_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_zephyr_user, gps_en_gpios, 0, __VA_ARGS__)
 
#define DT_N_S_zephyr_user_P_gps_en_gpios_LEN   1
 
#define DT_N_S_zephyr_user_P_gps_en_gpios_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_max_number   3
 
#define DT_N_S_zephyr_user_P_motor_max_number_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_VAL_pin   0
 
#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_VAL_flags   0
 
#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_zephyr_user, motor_d1m1_gpios, 0)
 
#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_zephyr_user, motor_d1m1_gpios, 0, __VA_ARGS__)
 
#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_LEN   1
 
#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_VAL_pin   1
 
#define DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_VAL_flags   0
 
#define DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d1com_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_zephyr_user, motor_d1com_gpios, 0)
 
#define DT_N_S_zephyr_user_P_motor_d1com_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_zephyr_user, motor_d1com_gpios, 0, __VA_ARGS__)
 
#define DT_N_S_zephyr_user_P_motor_d1com_gpios_LEN   1
 
#define DT_N_S_zephyr_user_P_motor_d1com_gpios_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_VAL_pin   2
 
#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_VAL_flags   0
 
#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_zephyr_user, motor_d1m2_gpios, 0)
 
#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_zephyr_user, motor_d1m2_gpios, 0, __VA_ARGS__)
 
#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_LEN   1
 
#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_VAL_pin   5
 
#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_VAL_flags   0
 
#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_zephyr_user, motor_d2m1_gpios, 0)
 
#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_zephyr_user, motor_d2m1_gpios, 0, __VA_ARGS__)
 
#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_LEN   1
 
#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_VAL_pin   4
 
#define DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_VAL_flags   0
 
#define DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d2com_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_zephyr_user, motor_d2com_gpios, 0)
 
#define DT_N_S_zephyr_user_P_motor_d2com_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_zephyr_user, motor_d2com_gpios, 0, __VA_ARGS__)
 
#define DT_N_S_zephyr_user_P_motor_d2com_gpios_LEN   1
 
#define DT_N_S_zephyr_user_P_motor_d2com_gpios_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_VAL_pin   3
 
#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_VAL_flags   0
 
#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_zephyr_user, motor_d2m2_gpios, 0)
 
#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_zephyr_user, motor_d2m2_gpios, 0, __VA_ARGS__)
 
#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_LEN   1
 
#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_EXISTS   1
 
#define DT_N_S_zephyr_user_P_led_max_number   3
 
#define DT_N_S_zephyr_user_P_led_max_number_EXISTS   1
 
#define DT_N_S_zephyr_user_P_button_max_number   3
 
#define DT_N_S_zephyr_user_P_button_max_number_EXISTS   1
 
#define DT_N_S_buttons_PATH   "/buttons"
 
#define DT_N_S_buttons_FULL_NAME   "buttons"
 
#define DT_N_S_buttons_PARENT   DT_N
 
#define DT_N_S_buttons_CHILD_IDX   8
 
#define DT_N_S_buttons_FOREACH_CHILD(fn)   fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2)
 
#define DT_N_S_buttons_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__)
 
#define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2)
 
#define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__)
 
#define DT_N_S_buttons_ORD   11
 
#define DT_N_S_buttons_REQUIRES_ORDS    0, /* / */
 
#define DT_N_S_buttons_SUPPORTS_ORDS
 
#define DT_N_S_buttons_EXISTS   1
 
#define DT_N_INST_0_gpio_keys   DT_N_S_buttons
 
#define DT_N_S_buttons_REG_NUM   0
 
#define DT_N_S_buttons_RANGES_NUM   0
 
#define DT_N_S_buttons_FOREACH_RANGE(fn)
 
#define DT_N_S_buttons_IRQ_NUM   0
 
#define DT_N_S_buttons_COMPAT_MATCHES_gpio_keys   1
 
#define DT_N_S_buttons_STATUS_okay   1
 
#define DT_N_S_buttons_PINCTRL_NUM   0
 
#define DT_N_S_buttons_P_compatible   {"gpio-keys"}
 
#define DT_N_S_buttons_P_compatible_IDX_0   "gpio-keys"
 
#define DT_N_S_buttons_P_compatible_IDX_0_TOKEN   gpio_keys
 
#define DT_N_S_buttons_P_compatible_IDX_0_UPPER_TOKEN   GPIO_KEYS
 
#define DT_N_S_buttons_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_buttons, compatible, 0)
 
#define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_buttons, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_buttons_P_compatible_LEN   1
 
#define DT_N_S_buttons_P_compatible_EXISTS   1
 
#define DT_N_S_buttons_S_button_0_PATH   "/buttons/button_0"
 
#define DT_N_S_buttons_S_button_0_FULL_NAME   "button_0"
 
#define DT_N_S_buttons_S_button_0_PARENT   DT_N_S_buttons
 
#define DT_N_S_buttons_S_button_0_CHILD_IDX   0
 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD(fn)
 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_buttons_S_button_0_ORD   12
 
#define DT_N_S_buttons_S_button_0_REQUIRES_ORDS
 
#define DT_N_S_buttons_S_button_0_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_buttons_S_button_0_EXISTS   1
 
#define DT_N_ALIAS_bt0   DT_N_S_buttons_S_button_0
 
#define DT_N_ALIAS_mcuboot_button0   DT_N_S_buttons_S_button_0
 
#define DT_N_NODELABEL_button0   DT_N_S_buttons_S_button_0
 
#define DT_N_S_buttons_S_button_0_REG_NUM   0
 
#define DT_N_S_buttons_S_button_0_RANGES_NUM   0
 
#define DT_N_S_buttons_S_button_0_FOREACH_RANGE(fn)
 
#define DT_N_S_buttons_S_button_0_IRQ_NUM   0
 
#define DT_N_S_buttons_S_button_0_STATUS_okay   1
 
#define DT_N_S_buttons_S_button_0_PINCTRL_NUM   0
 
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin   19
 
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags   17
 
#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_buttons_S_button_0, gpios, 0)
 
#define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_buttons_S_button_0, gpios, 0, __VA_ARGS__)
 
#define DT_N_S_buttons_S_button_0_P_gpios_LEN   1
 
#define DT_N_S_buttons_S_button_0_P_gpios_EXISTS   1
 
#define DT_N_S_buttons_S_button_0_P_label   "Push button 1"
 
#define DT_N_S_buttons_S_button_0_P_label_STRING_TOKEN   Push_button_1
 
#define DT_N_S_buttons_S_button_0_P_label_STRING_UPPER_TOKEN   PUSH_BUTTON_1
 
#define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_buttons_S_button_0_P_label_EXISTS   1
 
#define DT_N_S_buttons_S_button_1_PATH   "/buttons/button_1"
 
#define DT_N_S_buttons_S_button_1_FULL_NAME   "button_1"
 
#define DT_N_S_buttons_S_button_1_PARENT   DT_N_S_buttons
 
#define DT_N_S_buttons_S_button_1_CHILD_IDX   1
 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD(fn)
 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_buttons_S_button_1_ORD   13
 
#define DT_N_S_buttons_S_button_1_REQUIRES_ORDS
 
#define DT_N_S_buttons_S_button_1_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_buttons_S_button_1_EXISTS   1
 
#define DT_N_ALIAS_bt1   DT_N_S_buttons_S_button_1
 
#define DT_N_NODELABEL_button1   DT_N_S_buttons_S_button_1
 
#define DT_N_S_buttons_S_button_1_REG_NUM   0
 
#define DT_N_S_buttons_S_button_1_RANGES_NUM   0
 
#define DT_N_S_buttons_S_button_1_FOREACH_RANGE(fn)
 
#define DT_N_S_buttons_S_button_1_IRQ_NUM   0
 
#define DT_N_S_buttons_S_button_1_STATUS_okay   1
 
#define DT_N_S_buttons_S_button_1_PINCTRL_NUM   0
 
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin   18
 
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags   17
 
#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_buttons_S_button_1, gpios, 0)
 
#define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_buttons_S_button_1, gpios, 0, __VA_ARGS__)
 
#define DT_N_S_buttons_S_button_1_P_gpios_LEN   1
 
#define DT_N_S_buttons_S_button_1_P_gpios_EXISTS   1
 
#define DT_N_S_buttons_S_button_1_P_label   "Push button 2"
 
#define DT_N_S_buttons_S_button_1_P_label_STRING_TOKEN   Push_button_2
 
#define DT_N_S_buttons_S_button_1_P_label_STRING_UPPER_TOKEN   PUSH_BUTTON_2
 
#define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_buttons_S_button_1_P_label_EXISTS   1
 
#define DT_N_S_buttons_S_button_2_PATH   "/buttons/button_2"
 
#define DT_N_S_buttons_S_button_2_FULL_NAME   "button_2"
 
#define DT_N_S_buttons_S_button_2_PARENT   DT_N_S_buttons
 
#define DT_N_S_buttons_S_button_2_CHILD_IDX   2
 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD(fn)
 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_buttons_S_button_2_ORD   14
 
#define DT_N_S_buttons_S_button_2_REQUIRES_ORDS
 
#define DT_N_S_buttons_S_button_2_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_buttons_S_button_2_EXISTS   1
 
#define DT_N_ALIAS_bt2   DT_N_S_buttons_S_button_2
 
#define DT_N_NODELABEL_button2   DT_N_S_buttons_S_button_2
 
#define DT_N_S_buttons_S_button_2_REG_NUM   0
 
#define DT_N_S_buttons_S_button_2_RANGES_NUM   0
 
#define DT_N_S_buttons_S_button_2_FOREACH_RANGE(fn)
 
#define DT_N_S_buttons_S_button_2_IRQ_NUM   0
 
#define DT_N_S_buttons_S_button_2_STATUS_okay   1
 
#define DT_N_S_buttons_S_button_2_PINCTRL_NUM   0
 
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin   17
 
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags   17
 
#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_buttons_S_button_2, gpios, 0)
 
#define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_buttons_S_button_2, gpios, 0, __VA_ARGS__)
 
#define DT_N_S_buttons_S_button_2_P_gpios_LEN   1
 
#define DT_N_S_buttons_S_button_2_P_gpios_EXISTS   1
 
#define DT_N_S_buttons_S_button_2_P_label   "Switch 1"
 
#define DT_N_S_buttons_S_button_2_P_label_STRING_TOKEN   Switch_1
 
#define DT_N_S_buttons_S_button_2_P_label_STRING_UPPER_TOKEN   SWITCH_1
 
#define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_buttons_S_button_2_P_label_EXISTS   1
 
#define DT_N_S_cpus_PATH   "/cpus"
 
#define DT_N_S_cpus_FULL_NAME   "cpus"
 
#define DT_N_S_cpus_PARENT   DT_N
 
#define DT_N_S_cpus_CHILD_IDX   5
 
#define DT_N_S_cpus_FOREACH_CHILD(fn)   fn(DT_N_S_cpus_S_cpu_0)
 
#define DT_N_S_cpus_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
 
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_cpus_S_cpu_0)
 
#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
 
#define DT_N_S_cpus_ORD   15
 
#define DT_N_S_cpus_REQUIRES_ORDS    0, /* / */
 
#define DT_N_S_cpus_SUPPORTS_ORDS    16, /* /cpus/cpu@0 */
 
#define DT_N_S_cpus_EXISTS   1
 
#define DT_N_S_cpus_REG_NUM   0
 
#define DT_N_S_cpus_RANGES_NUM   0
 
#define DT_N_S_cpus_FOREACH_RANGE(fn)
 
#define DT_N_S_cpus_IRQ_NUM   0
 
#define DT_N_S_cpus_STATUS_okay   1
 
#define DT_N_S_cpus_PINCTRL_NUM   0
 
#define DT_N_S_cpus_S_cpu_0_PATH   "/cpus/cpu@0"
 
#define DT_N_S_cpus_S_cpu_0_FULL_NAME   "cpu@0"
 
#define DT_N_S_cpus_S_cpu_0_PARENT   DT_N_S_cpus
 
#define DT_N_S_cpus_S_cpu_0_CHILD_IDX   0
 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD(fn)   fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
 
#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
 
#define DT_N_S_cpus_S_cpu_0_ORD   16
 
#define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS    15, /* /cpus */
 
#define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS    17, /* /cpus/cpu@0/mpu@e000ed90 */
 
#define DT_N_S_cpus_S_cpu_0_EXISTS   1
 
#define DT_N_INST_0_arm_cortex_m33f   DT_N_S_cpus_S_cpu_0
 
#define DT_N_S_cpus_S_cpu_0_REG_NUM   1
 
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS   1
 
#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS   0 /* 0x0 */
 
#define DT_N_S_cpus_S_cpu_0_RANGES_NUM   0
 
#define DT_N_S_cpus_S_cpu_0_FOREACH_RANGE(fn)
 
#define DT_N_S_cpus_S_cpu_0_IRQ_NUM   0
 
#define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_arm_cortex_m33f   1
 
#define DT_N_S_cpus_S_cpu_0_STATUS_okay   1
 
#define DT_N_S_cpus_S_cpu_0_PINCTRL_NUM   0
 
#define DT_N_S_cpus_S_cpu_0_P_compatible   {"arm,cortex-m33f"}
 
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0   "arm,cortex-m33f"
 
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_TOKEN   arm_cortex_m33f
 
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_UPPER_TOKEN   ARM_CORTEX_M33F
 
#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_cpus_S_cpu_0, compatible, 0)
 
#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_cpus_S_cpu_0_P_compatible_LEN   1
 
#define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS   1
 
#define DT_N_S_cpus_S_cpu_0_P_reg   {0 /* 0x0 */}
 
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0   0
 
#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_cpus_S_cpu_0, reg, 0)
 
#define DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_cpus_S_cpu_0, reg, 0, __VA_ARGS__)
 
#define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS   1
 
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source   0
 
#define DT_N_S_cpus_S_cpu_0_P_wakeup_source_EXISTS   1
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PATH   "/cpus/cpu@0/mpu@e000ed90"
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FULL_NAME   "mpu@e000ed90"
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PARENT   DT_N_S_cpus_S_cpu_0
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_CHILD_IDX   0
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD(fn)
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD   17
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REQUIRES_ORDS    16, /* /cpus/cpu@0 */
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_EXISTS   1
 
#define DT_N_INST_0_arm_armv8m_mpu   DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90
 
#define DT_N_NODELABEL_mpu   DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_NUM   1
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_EXISTS   1
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_ADDRESS   3758157200 /* 0xe000ed90 */
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_SIZE   64 /* 0x40 */
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_RANGES_NUM   0
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_RANGE(fn)
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_IRQ_NUM   0
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MATCHES_arm_armv8m_mpu   1
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_STATUS_okay   1
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PINCTRL_NUM   0
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg   {3758157200 /* 0xe000ed90 */, 64 /* 0x40 */}
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0   3758157200
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1   64
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_EXISTS   1
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_arm_num_mpu_regions   16
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_arm_num_mpu_regions_EXISTS   1
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible   {"arm,armv8m-mpu"}
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0   "arm,armv8m-mpu"
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_TOKEN   arm_armv8m_mpu
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_UPPER_TOKEN   ARM_ARMV8M_MPU
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0)
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_LEN   1
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_EXISTS   1
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source   0
 
#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source_EXISTS   1
 
#define DT_N_S_leds_PATH   "/leds"
 
#define DT_N_S_leds_FULL_NAME   "leds"
 
#define DT_N_S_leds_PARENT   DT_N
 
#define DT_N_S_leds_CHILD_IDX   7
 
#define DT_N_S_leds_FOREACH_CHILD(fn)   fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2)
 
#define DT_N_S_leds_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__)
 
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2)
 
#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__)
 
#define DT_N_S_leds_ORD   18
 
#define DT_N_S_leds_REQUIRES_ORDS    0, /* / */
 
#define DT_N_S_leds_SUPPORTS_ORDS
 
#define DT_N_S_leds_EXISTS   1
 
#define DT_N_INST_0_gpio_leds   DT_N_S_leds
 
#define DT_N_S_leds_REG_NUM   0
 
#define DT_N_S_leds_RANGES_NUM   0
 
#define DT_N_S_leds_FOREACH_RANGE(fn)
 
#define DT_N_S_leds_IRQ_NUM   0
 
#define DT_N_S_leds_COMPAT_MATCHES_gpio_leds   1
 
#define DT_N_S_leds_STATUS_okay   1
 
#define DT_N_S_leds_PINCTRL_NUM   0
 
#define DT_N_S_leds_P_compatible   {"gpio-leds"}
 
#define DT_N_S_leds_P_compatible_IDX_0   "gpio-leds"
 
#define DT_N_S_leds_P_compatible_IDX_0_TOKEN   gpio_leds
 
#define DT_N_S_leds_P_compatible_IDX_0_UPPER_TOKEN   GPIO_LEDS
 
#define DT_N_S_leds_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_leds, compatible, 0)
 
#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_leds_P_compatible_LEN   1
 
#define DT_N_S_leds_P_compatible_EXISTS   1
 
#define DT_N_S_leds_S_led_0_PATH   "/leds/led_0"
 
#define DT_N_S_leds_S_led_0_FULL_NAME   "led_0"
 
#define DT_N_S_leds_S_led_0_PARENT   DT_N_S_leds
 
#define DT_N_S_leds_S_led_0_CHILD_IDX   0
 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD(fn)
 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_leds_S_led_0_ORD   19
 
#define DT_N_S_leds_S_led_0_REQUIRES_ORDS
 
#define DT_N_S_leds_S_led_0_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_leds_S_led_0_EXISTS   1
 
#define DT_N_ALIAS_led0   DT_N_S_leds_S_led_0
 
#define DT_N_ALIAS_bootloader_led0   DT_N_S_leds_S_led_0
 
#define DT_N_ALIAS_mcuboot_led0   DT_N_S_leds_S_led_0
 
#define DT_N_ALIAS_motord3m1   DT_N_S_leds_S_led_0
 
#define DT_N_NODELABEL_led0   DT_N_S_leds_S_led_0
 
#define DT_N_S_leds_S_led_0_REG_NUM   0
 
#define DT_N_S_leds_S_led_0_RANGES_NUM   0
 
#define DT_N_S_leds_S_led_0_FOREACH_RANGE(fn)
 
#define DT_N_S_leds_S_led_0_IRQ_NUM   0
 
#define DT_N_S_leds_S_led_0_STATUS_okay   1
 
#define DT_N_S_leds_S_led_0_PINCTRL_NUM   0
 
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin   15
 
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags   0
 
#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_leds_S_led_0, gpios, 0)
 
#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__)
 
#define DT_N_S_leds_S_led_0_P_gpios_LEN   1
 
#define DT_N_S_leds_S_led_0_P_gpios_EXISTS   1
 
#define DT_N_S_leds_S_led_0_P_label   "Green LED 1"
 
#define DT_N_S_leds_S_led_0_P_label_STRING_TOKEN   Green_LED_1
 
#define DT_N_S_leds_S_led_0_P_label_STRING_UPPER_TOKEN   GREEN_LED_1
 
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_leds_S_led_0_P_label_EXISTS   1
 
#define DT_N_S_leds_S_led_1_PATH   "/leds/led_1"
 
#define DT_N_S_leds_S_led_1_FULL_NAME   "led_1"
 
#define DT_N_S_leds_S_led_1_PARENT   DT_N_S_leds
 
#define DT_N_S_leds_S_led_1_CHILD_IDX   1
 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD(fn)
 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_leds_S_led_1_ORD   20
 
#define DT_N_S_leds_S_led_1_REQUIRES_ORDS
 
#define DT_N_S_leds_S_led_1_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_leds_S_led_1_EXISTS   1
 
#define DT_N_ALIAS_led1   DT_N_S_leds_S_led_1
 
#define DT_N_ALIAS_motord3com   DT_N_S_leds_S_led_1
 
#define DT_N_NODELABEL_led1   DT_N_S_leds_S_led_1
 
#define DT_N_S_leds_S_led_1_REG_NUM   0
 
#define DT_N_S_leds_S_led_1_RANGES_NUM   0
 
#define DT_N_S_leds_S_led_1_FOREACH_RANGE(fn)
 
#define DT_N_S_leds_S_led_1_IRQ_NUM   0
 
#define DT_N_S_leds_S_led_1_STATUS_okay   1
 
#define DT_N_S_leds_S_led_1_PINCTRL_NUM   0
 
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin   14
 
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags   0
 
#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_leds_S_led_1, gpios, 0)
 
#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_leds_S_led_1, gpios, 0, __VA_ARGS__)
 
#define DT_N_S_leds_S_led_1_P_gpios_LEN   1
 
#define DT_N_S_leds_S_led_1_P_gpios_EXISTS   1
 
#define DT_N_S_leds_S_led_1_P_label   "Green LED 2"
 
#define DT_N_S_leds_S_led_1_P_label_STRING_TOKEN   Green_LED_2
 
#define DT_N_S_leds_S_led_1_P_label_STRING_UPPER_TOKEN   GREEN_LED_2
 
#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_leds_S_led_1_P_label_EXISTS   1
 
#define DT_N_S_leds_S_led_2_PATH   "/leds/led_2"
 
#define DT_N_S_leds_S_led_2_FULL_NAME   "led_2"
 
#define DT_N_S_leds_S_led_2_PARENT   DT_N_S_leds
 
#define DT_N_S_leds_S_led_2_CHILD_IDX   2
 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD(fn)
 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_leds_S_led_2_ORD   21
 
#define DT_N_S_leds_S_led_2_REQUIRES_ORDS
 
#define DT_N_S_leds_S_led_2_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_leds_S_led_2_EXISTS   1
 
#define DT_N_ALIAS_led2   DT_N_S_leds_S_led_2
 
#define DT_N_ALIAS_motord3m2   DT_N_S_leds_S_led_2
 
#define DT_N_NODELABEL_led2   DT_N_S_leds_S_led_2
 
#define DT_N_S_leds_S_led_2_REG_NUM   0
 
#define DT_N_S_leds_S_led_2_RANGES_NUM   0
 
#define DT_N_S_leds_S_led_2_FOREACH_RANGE(fn)
 
#define DT_N_S_leds_S_led_2_IRQ_NUM   0
 
#define DT_N_S_leds_S_led_2_STATUS_okay   1
 
#define DT_N_S_leds_S_led_2_PINCTRL_NUM   0
 
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin   13
 
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags   0
 
#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_leds_S_led_2, gpios, 0)
 
#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_leds_S_led_2, gpios, 0, __VA_ARGS__)
 
#define DT_N_S_leds_S_led_2_P_gpios_LEN   1
 
#define DT_N_S_leds_S_led_2_P_gpios_EXISTS   1
 
#define DT_N_S_leds_S_led_2_P_label   "Green LED 3"
 
#define DT_N_S_leds_S_led_2_P_label_STRING_TOKEN   Green_LED_3
 
#define DT_N_S_leds_S_led_2_P_label_STRING_UPPER_TOKEN   GREEN_LED_3
 
#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_leds_S_led_2_P_label_EXISTS   1
 
#define DT_N_S_pin_controller_PATH   "/pin-controller"
 
#define DT_N_S_pin_controller_FULL_NAME   "pin-controller"
 
#define DT_N_S_pin_controller_PARENT   DT_N
 
#define DT_N_S_pin_controller_CHILD_IDX   3
 
#define DT_N_S_pin_controller_FOREACH_CHILD(fn)   fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart2_default) fn(DT_N_S_pin_controller_S_uart2_sleep) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_spi2_default) fn(DT_N_S_pin_controller_S_spi2_sleep)
 
#define DT_N_S_pin_controller_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_sleep, __VA_ARGS__)
 
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart2_default) fn(DT_N_S_pin_controller_S_uart2_sleep) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_spi2_default) fn(DT_N_S_pin_controller_S_spi2_sleep)
 
#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_sleep, __VA_ARGS__)
 
#define DT_N_S_pin_controller_ORD   22
 
#define DT_N_S_pin_controller_REQUIRES_ORDS    0, /* / */
 
#define DT_N_S_pin_controller_SUPPORTS_ORDS
 
#define DT_N_S_pin_controller_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_pinctrl   DT_N_S_pin_controller
 
#define DT_N_NODELABEL_pinctrl   DT_N_S_pin_controller
 
#define DT_N_S_pin_controller_REG_NUM   0
 
#define DT_N_S_pin_controller_RANGES_NUM   0
 
#define DT_N_S_pin_controller_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_IRQ_NUM   0
 
#define DT_N_S_pin_controller_COMPAT_MATCHES_nordic_nrf_pinctrl   1
 
#define DT_N_S_pin_controller_STATUS_okay   1
 
#define DT_N_S_pin_controller_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_P_compatible   {"nordic,nrf-pinctrl"}
 
#define DT_N_S_pin_controller_P_compatible_IDX_0   "nordic,nrf-pinctrl"
 
#define DT_N_S_pin_controller_P_compatible_IDX_0_TOKEN   nordic_nrf_pinctrl
 
#define DT_N_S_pin_controller_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_PINCTRL
 
#define DT_N_S_pin_controller_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_pin_controller, compatible, 0)
 
#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_pin_controller_P_compatible_LEN   1
 
#define DT_N_S_pin_controller_P_compatible_EXISTS   1
 
#define DT_N_S_pin_controller_P_wakeup_source   0
 
#define DT_N_S_pin_controller_P_wakeup_source_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_default_PATH   "/pin-controller/i2c1_default"
 
#define DT_N_S_pin_controller_S_i2c1_default_FULL_NAME   "i2c1_default"
 
#define DT_N_S_pin_controller_S_i2c1_default_PARENT   DT_N_S_pin_controller
 
#define DT_N_S_pin_controller_S_i2c1_default_CHILD_IDX   4
 
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD(fn)   fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)
 
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)
 
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_i2c1_default_ORD   23
 
#define DT_N_S_pin_controller_S_i2c1_default_REQUIRES_ORDS    22, /* /pin-controller */
 
#define DT_N_S_pin_controller_S_i2c1_default_SUPPORTS_ORDS
 
#define DT_N_S_pin_controller_S_i2c1_default_EXISTS   1
 
#define DT_N_NODELABEL_i2c1_default   DT_N_S_pin_controller_S_i2c1_default
 
#define DT_N_S_pin_controller_S_i2c1_default_REG_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_default_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_i2c1_default_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_default_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_i2c1_default_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_PATH   "/pin-controller/i2c1_default/group1"
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FULL_NAME   "group1"
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_PARENT   DT_N_S_pin_controller_S_i2c1_default
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_CHILD_IDX   0
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD(fn)
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_ORD   24
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_REQUIRES_ORDS    23, /* /pin-controller/i2c1_default */
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_REG_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels   {786440 /* 0xc0008 */, 720905 /* 0xb0009 */}
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_0   786440
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_0_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_1   720905
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_1_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_LEN   2
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_drive_mode   0
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_drive_mode_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_invert   0
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_invert_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_disable   0
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_disable_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_up   0
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_up_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_down   0
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_down_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_low_power_enable   0
 
#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_low_power_enable_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_sleep_PATH   "/pin-controller/i2c1_sleep"
 
#define DT_N_S_pin_controller_S_i2c1_sleep_FULL_NAME   "i2c1_sleep"
 
#define DT_N_S_pin_controller_S_i2c1_sleep_PARENT   DT_N_S_pin_controller
 
#define DT_N_S_pin_controller_S_i2c1_sleep_CHILD_IDX   5
 
#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD(fn)   fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1)
 
#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1)
 
#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_i2c1_sleep_ORD   25
 
#define DT_N_S_pin_controller_S_i2c1_sleep_REQUIRES_ORDS    22, /* /pin-controller */
 
#define DT_N_S_pin_controller_S_i2c1_sleep_SUPPORTS_ORDS
 
#define DT_N_S_pin_controller_S_i2c1_sleep_EXISTS   1
 
#define DT_N_NODELABEL_i2c1_sleep   DT_N_S_pin_controller_S_i2c1_sleep
 
#define DT_N_S_pin_controller_S_i2c1_sleep_REG_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_sleep_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_i2c1_sleep_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_sleep_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_i2c1_sleep_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PATH   "/pin-controller/i2c1_sleep/group1"
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FULL_NAME   "group1"
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PARENT   DT_N_S_pin_controller_S_i2c1_sleep
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_CHILD_IDX   0
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD(fn)
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_ORD   26
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_REQUIRES_ORDS    25, /* /pin-controller/i2c1_sleep */
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_REG_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels   {786440 /* 0xc0008 */, 720905 /* 0xb0009 */}
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_0   786440
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_0_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_1   720905
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_1_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_LEN   2
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_drive_mode   0
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_drive_mode_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_invert   0
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_invert_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_disable   0
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_disable_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_up   0
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_up_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_down   0
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_down_EXISTS   1
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_low_power_enable   1
 
#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_low_power_enable_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_default_PATH   "/pin-controller/spi2_default"
 
#define DT_N_S_pin_controller_S_spi2_default_FULL_NAME   "spi2_default"
 
#define DT_N_S_pin_controller_S_spi2_default_PARENT   DT_N_S_pin_controller
 
#define DT_N_S_pin_controller_S_spi2_default_CHILD_IDX   6
 
#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD(fn)   fn(DT_N_S_pin_controller_S_spi2_default_S_group1)
 
#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_spi2_default_S_group1, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_pin_controller_S_spi2_default_S_group1)
 
#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_spi2_default_S_group1, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_spi2_default_ORD   27
 
#define DT_N_S_pin_controller_S_spi2_default_REQUIRES_ORDS    22, /* /pin-controller */
 
#define DT_N_S_pin_controller_S_spi2_default_SUPPORTS_ORDS
 
#define DT_N_S_pin_controller_S_spi2_default_EXISTS   1
 
#define DT_N_NODELABEL_spi2_default   DT_N_S_pin_controller_S_spi2_default
 
#define DT_N_S_pin_controller_S_spi2_default_REG_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_default_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_default_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_spi2_default_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_default_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_spi2_default_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_PATH   "/pin-controller/spi2_default/group1"
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FULL_NAME   "group1"
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_PARENT   DT_N_S_pin_controller_S_spi2_default
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_CHILD_IDX   0
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD(fn)
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_ORD   28
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_REQUIRES_ORDS    27, /* /pin-controller/spi2_default */
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_REG_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels   {262174 /* 0x4001e */, 393245 /* 0x6001d */, 327711 /* 0x5001f */}
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_0   262174
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_0_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_1   393245
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_1_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_2   327711
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_2_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_LEN   3
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_drive_mode   0
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_drive_mode_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_invert   0
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_invert_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_disable   0
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_disable_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_up   0
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_up_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_down   0
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_down_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_low_power_enable   0
 
#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_low_power_enable_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_sleep_PATH   "/pin-controller/spi2_sleep"
 
#define DT_N_S_pin_controller_S_spi2_sleep_FULL_NAME   "spi2_sleep"
 
#define DT_N_S_pin_controller_S_spi2_sleep_PARENT   DT_N_S_pin_controller
 
#define DT_N_S_pin_controller_S_spi2_sleep_CHILD_IDX   7
 
#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD(fn)   fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1)
 
#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1)
 
#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_spi2_sleep_ORD   29
 
#define DT_N_S_pin_controller_S_spi2_sleep_REQUIRES_ORDS    22, /* /pin-controller */
 
#define DT_N_S_pin_controller_S_spi2_sleep_SUPPORTS_ORDS
 
#define DT_N_S_pin_controller_S_spi2_sleep_EXISTS   1
 
#define DT_N_NODELABEL_spi2_sleep   DT_N_S_pin_controller_S_spi2_sleep
 
#define DT_N_S_pin_controller_S_spi2_sleep_REG_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_sleep_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_spi2_sleep_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_sleep_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_spi2_sleep_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_PATH   "/pin-controller/spi2_sleep/group1"
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FULL_NAME   "group1"
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_PARENT   DT_N_S_pin_controller_S_spi2_sleep
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_CHILD_IDX   0
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD(fn)
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_ORD   30
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_REQUIRES_ORDS    29, /* /pin-controller/spi2_sleep */
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_REG_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels   {262174 /* 0x4001e */, 393245 /* 0x6001d */, 327711 /* 0x5001f */}
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_0   262174
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_0_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_1   393245
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_1_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_2   327711
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_2_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_LEN   3
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_drive_mode   0
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_drive_mode_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_invert   0
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_invert_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_disable   0
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_disable_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_up   0
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_up_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_down   0
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_down_EXISTS   1
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_low_power_enable   1
 
#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_low_power_enable_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_PATH   "/pin-controller/uart0_default"
 
#define DT_N_S_pin_controller_S_uart0_default_FULL_NAME   "uart0_default"
 
#define DT_N_S_pin_controller_S_uart0_default_PARENT   DT_N_S_pin_controller
 
#define DT_N_S_pin_controller_S_uart0_default_CHILD_IDX   0
 
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD(fn)   fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2)
 
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2)
 
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_uart0_default_ORD   31
 
#define DT_N_S_pin_controller_S_uart0_default_REQUIRES_ORDS    22, /* /pin-controller */
 
#define DT_N_S_pin_controller_S_uart0_default_SUPPORTS_ORDS
 
#define DT_N_S_pin_controller_S_uart0_default_EXISTS   1
 
#define DT_N_NODELABEL_uart0_default   DT_N_S_pin_controller_S_uart0_default
 
#define DT_N_S_pin_controller_S_uart0_default_REG_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_default_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_default_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_uart0_default_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_default_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_uart0_default_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_PATH   "/pin-controller/uart0_default/group1"
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FULL_NAME   "group1"
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_PARENT   DT_N_S_pin_controller_S_uart0_default
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_IDX   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD(fn)
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_ORD   32
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_REQUIRES_ORDS    31, /* /pin-controller/uart0_default */
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_REG_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels   {6 /* 0x6 */}
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0   6
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0)
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_LEN   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_PATH   "/pin-controller/uart0_default/group2"
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FULL_NAME   "group2"
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_PARENT   DT_N_S_pin_controller_S_uart0_default
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_IDX   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD(fn)
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_ORD   33
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_REQUIRES_ORDS    31, /* /pin-controller/uart0_default */
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_REG_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels   {65543 /* 0x10007 */}
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_0   65543
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_0_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0)
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_LEN   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_drive_mode   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_drive_mode_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_invert   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_invert_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_low_power_enable   0
 
#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_low_power_enable_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_sleep_PATH   "/pin-controller/uart0_sleep"
 
#define DT_N_S_pin_controller_S_uart0_sleep_FULL_NAME   "uart0_sleep"
 
#define DT_N_S_pin_controller_S_uart0_sleep_PARENT   DT_N_S_pin_controller
 
#define DT_N_S_pin_controller_S_uart0_sleep_CHILD_IDX   1
 
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD(fn)   fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)
 
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)
 
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_uart0_sleep_ORD   34
 
#define DT_N_S_pin_controller_S_uart0_sleep_REQUIRES_ORDS    22, /* /pin-controller */
 
#define DT_N_S_pin_controller_S_uart0_sleep_SUPPORTS_ORDS
 
#define DT_N_S_pin_controller_S_uart0_sleep_EXISTS   1
 
#define DT_N_NODELABEL_uart0_sleep   DT_N_S_pin_controller_S_uart0_sleep
 
#define DT_N_S_pin_controller_S_uart0_sleep_REG_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_sleep_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_uart0_sleep_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_sleep_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_uart0_sleep_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PATH   "/pin-controller/uart0_sleep/group1"
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FULL_NAME   "group1"
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PARENT   DT_N_S_pin_controller_S_uart0_sleep
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_CHILD_IDX   0
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD(fn)
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_ORD   35
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_REQUIRES_ORDS    34, /* /pin-controller/uart0_sleep */
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_REG_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels   {6 /* 0x6 */, 65543 /* 0x10007 */}
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0   6
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1   65543
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_LEN   2
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode   0
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert   0
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable   0
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up   0
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down   0
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable   1
 
#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_default_PATH   "/pin-controller/uart2_default"
 
#define DT_N_S_pin_controller_S_uart2_default_FULL_NAME   "uart2_default"
 
#define DT_N_S_pin_controller_S_uart2_default_PARENT   DT_N_S_pin_controller
 
#define DT_N_S_pin_controller_S_uart2_default_CHILD_IDX   2
 
#define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD(fn)   fn(DT_N_S_pin_controller_S_uart2_default_S_group1)
 
#define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_uart2_default_S_group1, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_pin_controller_S_uart2_default_S_group1)
 
#define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_uart2_default_S_group1, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_uart2_default_ORD   36
 
#define DT_N_S_pin_controller_S_uart2_default_REQUIRES_ORDS    22, /* /pin-controller */
 
#define DT_N_S_pin_controller_S_uart2_default_SUPPORTS_ORDS
 
#define DT_N_S_pin_controller_S_uart2_default_EXISTS   1
 
#define DT_N_NODELABEL_uart2_default   DT_N_S_pin_controller_S_uart2_default
 
#define DT_N_S_pin_controller_S_uart2_default_REG_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_default_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_default_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_uart2_default_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_default_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_uart2_default_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_PATH   "/pin-controller/uart2_default/group1"
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_FULL_NAME   "group1"
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_PARENT   DT_N_S_pin_controller_S_uart2_default
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_CHILD_IDX   0
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD(fn)
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_ORD   37
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_REQUIRES_ORDS    36, /* /pin-controller/uart2_default */
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_REG_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels   {24 /* 0x18 */, 65559 /* 0x10017 */}
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_0   24
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_0_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_1   65559
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_1_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_LEN   2
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_drive_mode   0
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_drive_mode_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_invert   0
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_invert_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_disable   0
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_disable_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_up   0
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_up_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_down   0
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_down_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_low_power_enable   0
 
#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_low_power_enable_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_sleep_PATH   "/pin-controller/uart2_sleep"
 
#define DT_N_S_pin_controller_S_uart2_sleep_FULL_NAME   "uart2_sleep"
 
#define DT_N_S_pin_controller_S_uart2_sleep_PARENT   DT_N_S_pin_controller
 
#define DT_N_S_pin_controller_S_uart2_sleep_CHILD_IDX   3
 
#define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD(fn)   fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1)
 
#define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1)
 
#define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, __VA_ARGS__)
 
#define DT_N_S_pin_controller_S_uart2_sleep_ORD   38
 
#define DT_N_S_pin_controller_S_uart2_sleep_REQUIRES_ORDS    22, /* /pin-controller */
 
#define DT_N_S_pin_controller_S_uart2_sleep_SUPPORTS_ORDS
 
#define DT_N_S_pin_controller_S_uart2_sleep_EXISTS   1
 
#define DT_N_NODELABEL_uart2_sleep   DT_N_S_pin_controller_S_uart2_sleep
 
#define DT_N_S_pin_controller_S_uart2_sleep_REG_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_sleep_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_uart2_sleep_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_sleep_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_uart2_sleep_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_PATH   "/pin-controller/uart2_sleep/group1"
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FULL_NAME   "group1"
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_PARENT   DT_N_S_pin_controller_S_uart2_sleep
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_CHILD_IDX   0
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD(fn)
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_ORD   39
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_REQUIRES_ORDS    38, /* /pin-controller/uart2_sleep */
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_REG_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_RANGES_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_RANGE(fn)
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_IRQ_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_STATUS_okay   1
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_PINCTRL_NUM   0
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels   {24 /* 0x18 */, 65559 /* 0x10017 */}
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_0   24
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_0_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_1   65559
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_1_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_LEN   2
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_drive_mode   0
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_drive_mode_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_invert   0
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_invert_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_disable   0
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_disable_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_up   0
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_up_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_down   0
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_down_EXISTS   1
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_low_power_enable   1
 
#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_low_power_enable_EXISTS   1
 
#define DT_N_S_reserved_memory_PATH   "/reserved-memory"
 
#define DT_N_S_reserved_memory_FULL_NAME   "reserved-memory"
 
#define DT_N_S_reserved_memory_PARENT   DT_N
 
#define DT_N_S_reserved_memory_CHILD_IDX   9
 
#define DT_N_S_reserved_memory_FOREACH_CHILD(fn)   fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_modem_20016000) fn(DT_N_S_reserved_memory_S_image_ns_20020000)
 
#define DT_N_S_reserved_memory_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_modem_20016000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20020000, __VA_ARGS__)
 
#define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_modem_20016000) fn(DT_N_S_reserved_memory_S_image_ns_20020000)
 
#define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_modem_20016000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20020000, __VA_ARGS__)
 
#define DT_N_S_reserved_memory_ORD   40
 
#define DT_N_S_reserved_memory_REQUIRES_ORDS    0, /* / */
 
#define DT_N_S_reserved_memory_SUPPORTS_ORDS
 
#define DT_N_S_reserved_memory_EXISTS   1
 
#define DT_N_S_reserved_memory_REG_NUM   0
 
#define DT_N_S_reserved_memory_RANGES_NUM   0
 
#define DT_N_S_reserved_memory_FOREACH_RANGE(fn)
 
#define DT_N_S_reserved_memory_IRQ_NUM   0
 
#define DT_N_S_reserved_memory_STATUS_okay   1
 
#define DT_N_S_reserved_memory_PINCTRL_NUM   0
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_PATH   "/reserved-memory/image_modem@20016000"
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_FULL_NAME   "image_modem@20016000"
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_PARENT   DT_N_S_reserved_memory
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_CHILD_IDX   1
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD(fn)
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_ORD   41
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_REQUIRES_ORDS    40, /* /reserved-memory */
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_EXISTS   1
 
#define DT_N_NODELABEL_sram0_modem   DT_N_S_reserved_memory_S_image_modem_20016000
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_REG_NUM   1
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_REG_IDX_0_VAL_ADDRESS   536961024 /* 0x20016000 */
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_REG_IDX_0_VAL_SIZE   40960 /* 0xa000 */
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_RANGES_NUM   0
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_RANGE(fn)
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_IRQ_NUM   0
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_STATUS_okay   1
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_PINCTRL_NUM   0
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg   {536961024 /* 0x20016000 */, 40960 /* 0xa000 */}
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_0   536961024
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_1   40960
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_EXISTS   1
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_PATH   "/reserved-memory/image_ns@20020000"
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_FULL_NAME   "image_ns@20020000"
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_PARENT   DT_N_S_reserved_memory
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_CHILD_IDX   2
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD(fn)
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_ORD   42
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_REQUIRES_ORDS    40, /* /reserved-memory */
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_EXISTS   1
 
#define DT_N_NODELABEL_sram0_ns   DT_N_S_reserved_memory_S_image_ns_20020000
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_NUM   1
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_VAL_ADDRESS   537001984 /* 0x20020000 */
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_VAL_SIZE   131072 /* 0x20000 */
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_RANGES_NUM   0
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_RANGE(fn)
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_IRQ_NUM   0
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_STATUS_okay   1
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_PINCTRL_NUM   0
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg   {537001984 /* 0x20020000 */, 131072 /* 0x20000 */}
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_0   537001984
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_1   131072
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_EXISTS   1
 
#define DT_N_S_reserved_memory_S_image_s_20000000_PATH   "/reserved-memory/image_s@20000000"
 
#define DT_N_S_reserved_memory_S_image_s_20000000_FULL_NAME   "image_s@20000000"
 
#define DT_N_S_reserved_memory_S_image_s_20000000_PARENT   DT_N_S_reserved_memory
 
#define DT_N_S_reserved_memory_S_image_s_20000000_CHILD_IDX   0
 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD(fn)
 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_reserved_memory_S_image_s_20000000_ORD   43
 
#define DT_N_S_reserved_memory_S_image_s_20000000_REQUIRES_ORDS    40, /* /reserved-memory */
 
#define DT_N_S_reserved_memory_S_image_s_20000000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_reserved_memory_S_image_s_20000000_EXISTS   1
 
#define DT_N_NODELABEL_sram0_s   DT_N_S_reserved_memory_S_image_s_20000000
 
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_NUM   1
 
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_ADDRESS   536870912 /* 0x20000000 */
 
#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_SIZE   90112 /* 0x16000 */
 
#define DT_N_S_reserved_memory_S_image_s_20000000_RANGES_NUM   0
 
#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_RANGE(fn)
 
#define DT_N_S_reserved_memory_S_image_s_20000000_IRQ_NUM   0
 
#define DT_N_S_reserved_memory_S_image_s_20000000_STATUS_okay   1
 
#define DT_N_S_reserved_memory_S_image_s_20000000_PINCTRL_NUM   0
 
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg   {536870912 /* 0x20000000 */, 90112 /* 0x16000 */}
 
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0   536870912
 
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1   90112
 
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_gpiote_40031000_PATH   "/soc/gpiote@40031000"
 
#define DT_N_S_soc_S_gpiote_40031000_FULL_NAME   "gpiote@40031000"
 
#define DT_N_S_soc_S_gpiote_40031000_PARENT   DT_N_S_soc
 
#define DT_N_S_soc_S_gpiote_40031000_CHILD_IDX   4
 
#define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_gpiote_40031000_ORD   44
 
#define DT_N_S_soc_S_gpiote_40031000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_gpiote_40031000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_gpiote_40031000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_gpiote   DT_N_S_soc_S_gpiote_40031000
 
#define DT_N_NODELABEL_gpiote   DT_N_S_soc_S_gpiote_40031000
 
#define DT_N_S_soc_S_gpiote_40031000_REG_NUM   1
 
#define DT_N_S_soc_S_gpiote_40031000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_gpiote_40031000_REG_IDX_0_VAL_ADDRESS   1073942528 /* 0x40031000 */
 
#define DT_N_S_soc_S_gpiote_40031000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_gpiote_40031000_RANGES_NUM   0
 
#define DT_N_S_soc_S_gpiote_40031000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_gpiote_40031000_IRQ_NUM   1
 
#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_irq   49
 
#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_priority   5
 
#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_gpiote_40031000_COMPAT_MATCHES_nordic_nrf_gpiote   1
 
#define DT_N_S_soc_S_gpiote_40031000_STATUS_okay   1
 
#define DT_N_S_soc_S_gpiote_40031000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_gpiote_40031000_P_reg   {1073942528 /* 0x40031000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_0   1073942528
 
#define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_gpiote_40031000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_gpiote_40031000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_gpiote_40031000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_gpiote_40031000_P_interrupts   {49 /* 0x31 */, 5 /* 0x5 */}
 
#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_0   49
 
#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_1   5
 
#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_gpiote_40031000_P_status   "okay"
 
#define DT_N_S_soc_S_gpiote_40031000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_gpiote_40031000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_gpiote_40031000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_gpiote_40031000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_gpiote_40031000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_gpiote_40031000_P_compatible   {"nordic,nrf-gpiote"}
 
#define DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0   "nordic,nrf-gpiote"
 
#define DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0_TOKEN   nordic_nrf_gpiote
 
#define DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_GPIOTE
 
#define DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_gpiote_40031000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_gpiote_40031000, compatible, 0)
 
#define DT_N_S_soc_S_gpiote_40031000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_gpiote_40031000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_gpiote_40031000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_gpiote_40031000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_gpiote_40031000_P_wakeup_source   0
 
#define DT_N_S_soc_S_gpiote_40031000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_memory_20000000_PATH   "/soc/memory@20000000"
 
#define DT_N_S_soc_S_memory_20000000_FULL_NAME   "memory@20000000"
 
#define DT_N_S_soc_S_memory_20000000_PARENT   DT_N_S_soc
 
#define DT_N_S_soc_S_memory_20000000_CHILD_IDX   2
 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_memory_20000000_ORD   45
 
#define DT_N_S_soc_S_memory_20000000_REQUIRES_ORDS    5, /* /soc */
 
#define DT_N_S_soc_S_memory_20000000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_memory_20000000_EXISTS   1
 
#define DT_N_INST_0_mmio_sram   DT_N_S_soc_S_memory_20000000
 
#define DT_N_NODELABEL_sram0   DT_N_S_soc_S_memory_20000000
 
#define DT_N_S_soc_S_memory_20000000_REG_NUM   1
 
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_ADDRESS   536870912 /* 0x20000000 */
 
#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_SIZE   262144 /* 0x40000 */
 
#define DT_N_S_soc_S_memory_20000000_RANGES_NUM   0
 
#define DT_N_S_soc_S_memory_20000000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_memory_20000000_IRQ_NUM   0
 
#define DT_N_S_soc_S_memory_20000000_COMPAT_MATCHES_mmio_sram   1
 
#define DT_N_S_soc_S_memory_20000000_STATUS_okay   1
 
#define DT_N_S_soc_S_memory_20000000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_memory_20000000_P_reg   {536870912 /* 0x20000000 */, 262144 /* 0x40000 */}
 
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0   536870912
 
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1   262144
 
#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_memory_20000000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_memory_20000000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_memory_20000000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_memory_20000000_P_compatible   {"mmio-sram"}
 
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0   "mmio-sram"
 
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_TOKEN   mmio_sram
 
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_UPPER_TOKEN   MMIO_SRAM
 
#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_memory_20000000, compatible, 0)
 
#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_memory_20000000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_memory_20000000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_memory_20000000_P_wakeup_source   0
 
#define DT_N_S_soc_S_memory_20000000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_timer_e000e010_PATH   "/soc/timer@e000e010"
 
#define DT_N_S_soc_S_timer_e000e010_FULL_NAME   "timer@e000e010"
 
#define DT_N_S_soc_S_timer_e000e010_PARENT   DT_N_S_soc
 
#define DT_N_S_soc_S_timer_e000e010_CHILD_IDX   1
 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_timer_e000e010_ORD   46
 
#define DT_N_S_soc_S_timer_e000e010_REQUIRES_ORDS    5, /* /soc */
 
#define DT_N_S_soc_S_timer_e000e010_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_timer_e000e010_EXISTS   1
 
#define DT_N_INST_0_arm_armv8m_systick   DT_N_S_soc_S_timer_e000e010
 
#define DT_N_NODELABEL_systick   DT_N_S_soc_S_timer_e000e010
 
#define DT_N_S_soc_S_timer_e000e010_REG_NUM   1
 
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS   3758153744 /* 0xe000e010 */
 
#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE   16 /* 0x10 */
 
#define DT_N_S_soc_S_timer_e000e010_RANGES_NUM   0
 
#define DT_N_S_soc_S_timer_e000e010_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_timer_e000e010_IRQ_NUM   0
 
#define DT_N_S_soc_S_timer_e000e010_COMPAT_MATCHES_arm_armv8m_systick   1
 
#define DT_N_S_soc_S_timer_e000e010_STATUS_disabled   1
 
#define DT_N_S_soc_S_timer_e000e010_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_timer_e000e010_P_compatible   {"arm,armv8m-systick"}
 
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0   "arm,armv8m-systick"
 
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_TOKEN   arm_armv8m_systick
 
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_UPPER_TOKEN   ARM_ARMV8M_SYSTICK
 
#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_timer_e000e010, compatible, 0)
 
#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_timer_e000e010_P_compatible_LEN   1
 
#define DT_N_S_soc_S_timer_e000e010_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_timer_e000e010_P_reg   {3758153744 /* 0xe000e010 */, 16 /* 0x10 */}
 
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0   3758153744
 
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1   16
 
#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_timer_e000e010_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_timer_e000e010_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_timer_e000e010_P_status   "disabled"
 
#define DT_N_S_soc_S_timer_e000e010_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_timer_e000e010_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_timer_e000e010_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_PATH   "/soc/peripheral@40000000/clock@5000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FULL_NAME   "clock@5000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_CHILD_IDX   34
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_ORD   47
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_clock   DT_N_S_soc_S_peripheral_40000000_S_clock_5000
 
#define DT_N_NODELABEL_clock   DT_N_S_soc_S_peripheral_40000000_S_clock_5000
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_IDX_0_VAL_ADDRESS   1073762304 /* 0x40005000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_irq   5
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_COMPAT_MATCHES_nordic_nrf_clock   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg   {20480 /* 0x5000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_0   20480
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts   {5 /* 0x5 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_0   5
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible   {"nordic,nrf-clock"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_IDX_0   "nordic,nrf-clock"
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_IDX_0_TOKEN   nordic_nrf_clock
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_CLOCK
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_PATH   "/soc/peripheral@40000000/dppic@17000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FULL_NAME   "dppic@17000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_CHILD_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_ORD   48
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REQUIRES_ORDS    7, /* /soc/peripheral@40000000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_dppic   DT_N_S_soc_S_peripheral_40000000_S_dppic_17000
 
#define DT_N_NODELABEL_dppic   DT_N_S_soc_S_peripheral_40000000_S_dppic_17000
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_IDX_0_VAL_ADDRESS   1073836032 /* 0x40017000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_COMPAT_MATCHES_nordic_nrf_dppic   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg   {94208 /* 0x17000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_0   94208
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible   {"nordic,nrf-dppic"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_IDX_0   "nordic,nrf-dppic"
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_IDX_0_TOKEN   nordic_nrf_dppic
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_DPPIC
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_PATH   "/soc/peripheral@40000000/egu@1b000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FULL_NAME   "egu@1b000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_CHILD_IDX   3
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_ORD   49
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_egu   DT_N_S_soc_S_peripheral_40000000_S_egu_1b000
 
#define DT_N_NODELABEL_egu0   DT_N_S_soc_S_peripheral_40000000_S_egu_1b000
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_IDX_0_VAL_ADDRESS   1073852416 /* 0x4001b000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_irq   27
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_COMPAT_MATCHES_nordic_nrf_egu   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg   {110592 /* 0x1b000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_0   110592
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts   {27 /* 0x1b */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_0   27
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible   {"nordic,nrf-egu"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_IDX_0   "nordic,nrf-egu"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_IDX_0_TOKEN   nordic_nrf_egu
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_EGU
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_PATH   "/soc/peripheral@40000000/egu@1c000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FULL_NAME   "egu@1c000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_CHILD_IDX   4
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_ORD   50
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_EXISTS   1
 
#define DT_N_INST_1_nordic_nrf_egu   DT_N_S_soc_S_peripheral_40000000_S_egu_1c000
 
#define DT_N_NODELABEL_egu1   DT_N_S_soc_S_peripheral_40000000_S_egu_1c000
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_IDX_0_VAL_ADDRESS   1073856512 /* 0x4001c000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_irq   28
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_COMPAT_MATCHES_nordic_nrf_egu   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg   {114688 /* 0x1c000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_0   114688
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts   {28 /* 0x1c */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_0   28
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible   {"nordic,nrf-egu"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_IDX_0   "nordic,nrf-egu"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_IDX_0_TOKEN   nordic_nrf_egu
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_EGU
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_PATH   "/soc/peripheral@40000000/egu@1d000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FULL_NAME   "egu@1d000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_CHILD_IDX   5
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_ORD   51
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_EXISTS   1
 
#define DT_N_INST_2_nordic_nrf_egu   DT_N_S_soc_S_peripheral_40000000_S_egu_1d000
 
#define DT_N_NODELABEL_egu2   DT_N_S_soc_S_peripheral_40000000_S_egu_1d000
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_IDX_0_VAL_ADDRESS   1073860608 /* 0x4001d000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_irq   29
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_COMPAT_MATCHES_nordic_nrf_egu   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg   {118784 /* 0x1d000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_0   118784
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts   {29 /* 0x1d */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_0   29
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible   {"nordic,nrf-egu"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_IDX_0   "nordic,nrf-egu"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_IDX_0_TOKEN   nordic_nrf_egu
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_EGU
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_PATH   "/soc/peripheral@40000000/egu@1e000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FULL_NAME   "egu@1e000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_CHILD_IDX   6
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_ORD   52
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_EXISTS   1
 
#define DT_N_INST_3_nordic_nrf_egu   DT_N_S_soc_S_peripheral_40000000_S_egu_1e000
 
#define DT_N_NODELABEL_egu3   DT_N_S_soc_S_peripheral_40000000_S_egu_1e000
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_IDX_0_VAL_ADDRESS   1073864704 /* 0x4001e000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_irq   30
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_COMPAT_MATCHES_nordic_nrf_egu   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg   {122880 /* 0x1e000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_0   122880
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts   {30 /* 0x1e */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_0   30
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible   {"nordic,nrf-egu"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_IDX_0   "nordic,nrf-egu"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_IDX_0_TOKEN   nordic_nrf_egu
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_EGU
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_PATH   "/soc/peripheral@40000000/egu@1f000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FULL_NAME   "egu@1f000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_CHILD_IDX   7
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_ORD   53
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_EXISTS   1
 
#define DT_N_INST_4_nordic_nrf_egu   DT_N_S_soc_S_peripheral_40000000_S_egu_1f000
 
#define DT_N_NODELABEL_egu4   DT_N_S_soc_S_peripheral_40000000_S_egu_1f000
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_IDX_0_VAL_ADDRESS   1073868800 /* 0x4001f000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_irq   31
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_COMPAT_MATCHES_nordic_nrf_egu   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg   {126976 /* 0x1f000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_0   126976
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts   {31 /* 0x1f */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_0   31
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible   {"nordic,nrf-egu"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_IDX_0   "nordic,nrf-egu"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_IDX_0_TOKEN   nordic_nrf_egu
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_EGU
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_PATH   "/soc/peripheral@40000000/egu@20000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FULL_NAME   "egu@20000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_CHILD_IDX   8
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_ORD   54
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_EXISTS   1
 
#define DT_N_INST_5_nordic_nrf_egu   DT_N_S_soc_S_peripheral_40000000_S_egu_20000
 
#define DT_N_NODELABEL_egu5   DT_N_S_soc_S_peripheral_40000000_S_egu_20000
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_IDX_0_VAL_ADDRESS   1073872896 /* 0x40020000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_irq   32
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_COMPAT_MATCHES_nordic_nrf_egu   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg   {131072 /* 0x20000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_0   131072
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts   {32 /* 0x20 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_0   32
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible   {"nordic,nrf-egu"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_IDX_0   "nordic,nrf-egu"
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_IDX_0_TOKEN   nordic_nrf_egu
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_EGU
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_PATH   "/soc/peripheral@40000000/i2c@8000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FULL_NAME   "i2c@8000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_CHILD_IDX   19
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_ORD   55
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_EXISTS   1
 
#define DT_N_INST_1_nordic_nrf_twim   DT_N_S_soc_S_peripheral_40000000_S_i2c_8000
 
#define DT_N_NODELABEL_i2c0   DT_N_S_soc_S_peripheral_40000000_S_i2c_8000
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_IDX_0_VAL_ADDRESS   1073774592 /* 0x40008000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_irq   8
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_COMPAT_MATCHES_nordic_nrf_twim   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_STATUS_disabled   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_zephyr_concat_buf_size   16
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_zephyr_concat_buf_size_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_zephyr_flash_buf_max_size   16
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_zephyr_flash_buf_max_size_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg   {32768 /* 0x8000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_0   32768
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts   {8 /* 0x8 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_0   8
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_clock_frequency   100000
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_clock_frequency_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status   "disabled"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible   {"nordic,nrf-twim"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_IDX_0   "nordic,nrf-twim"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_IDX_0_TOKEN   nordic_nrf_twim
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_TWIM
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PATH   "/soc/peripheral@40000000/i2c@9000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FULL_NAME   "i2c@9000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_CHILD_IDX   20
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_ORD   56
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_twim   DT_N_S_soc_S_peripheral_40000000_S_i2c_9000
 
#define DT_N_NODELABEL_i2c1   DT_N_S_soc_S_peripheral_40000000_S_i2c_9000
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_IDX_0_VAL_ADDRESS   1073778688 /* 0x40009000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_irq   9
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_COMPAT_MATCHES_nordic_nrf_twim   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NUM   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_0_TOKEN   default
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_0_UPPER_TOKEN   DEFAULT
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_default_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_default_IDX   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_default_IDX_0_PH   DT_N_S_pin_controller_S_i2c1_default
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_1_TOKEN   sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_1_UPPER_TOKEN   SLEEP
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_sleep_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_sleep_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_sleep_IDX_0_PH   DT_N_S_pin_controller_S_i2c1_sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_zephyr_concat_buf_size   16
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_zephyr_concat_buf_size_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_zephyr_flash_buf_max_size   16
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_zephyr_flash_buf_max_size_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg   {36864 /* 0x9000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_0   36864
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts   {9 /* 0x9 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_0   9
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_clock_frequency   100000
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_clock_frequency_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible   {"nordic,nrf-twim"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_IDX_0   "nordic,nrf-twim"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_IDX_0_TOKEN   nordic_nrf_twim
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_TWIM
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_IDX_0   DT_N_S_pin_controller_S_i2c1_default
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_IDX_0_PH   DT_N_S_pin_controller_S_i2c1_default
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, pinctrl_0, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, pinctrl_0, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_IDX_0   DT_N_S_pin_controller_S_i2c1_sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_IDX_0_PH   DT_N_S_pin_controller_S_i2c1_sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, pinctrl_1, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, pinctrl_1, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names   {"default", "sleep"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_0   "default"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_0_TOKEN   default
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_0_UPPER_TOKEN   DEFAULT
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_1   "sleep"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_1_TOKEN   sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_1_UPPER_TOKEN   SLEEP
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_LEN   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_PATH   "/soc/peripheral@40000000/i2c@a000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FULL_NAME   "i2c@a000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_CHILD_IDX   21
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_ORD   57
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_EXISTS   1
 
#define DT_N_INST_2_nordic_nrf_twim   DT_N_S_soc_S_peripheral_40000000_S_i2c_a000
 
#define DT_N_NODELABEL_i2c2   DT_N_S_soc_S_peripheral_40000000_S_i2c_a000
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_IDX_0_VAL_ADDRESS   1073782784 /* 0x4000a000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_irq   10
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_COMPAT_MATCHES_nordic_nrf_twim   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_STATUS_disabled   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_zephyr_concat_buf_size   16
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_zephyr_concat_buf_size_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_zephyr_flash_buf_max_size   16
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_zephyr_flash_buf_max_size_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg   {40960 /* 0xa000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_0   40960
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts   {10 /* 0xa */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_0   10
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_clock_frequency   100000
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_clock_frequency_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status   "disabled"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible   {"nordic,nrf-twim"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_IDX_0   "nordic,nrf-twim"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_IDX_0_TOKEN   nordic_nrf_twim
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_TWIM
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_PATH   "/soc/peripheral@40000000/i2c@b000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FULL_NAME   "i2c@b000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_CHILD_IDX   22
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_ORD   58
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_EXISTS   1
 
#define DT_N_INST_3_nordic_nrf_twim   DT_N_S_soc_S_peripheral_40000000_S_i2c_b000
 
#define DT_N_NODELABEL_i2c3   DT_N_S_soc_S_peripheral_40000000_S_i2c_b000
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_IDX_0_VAL_ADDRESS   1073786880 /* 0x4000b000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_irq   11
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_COMPAT_MATCHES_nordic_nrf_twim   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_STATUS_disabled   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_zephyr_concat_buf_size   16
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_zephyr_concat_buf_size_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_zephyr_flash_buf_max_size   16
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_zephyr_flash_buf_max_size_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg   {45056 /* 0xb000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_0   45056
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts   {11 /* 0xb */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_0   11
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_clock_frequency   100000
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_clock_frequency_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status   "disabled"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible   {"nordic,nrf-twim"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_IDX_0   "nordic,nrf-twim"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_IDX_0_TOKEN   nordic_nrf_twim
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_TWIM
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_PATH   "/soc/peripheral@40000000/i2s@28000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FULL_NAME   "i2s@28000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_CHILD_IDX   10
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_ORD   59
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_i2s   DT_N_S_soc_S_peripheral_40000000_S_i2s_28000
 
#define DT_N_NODELABEL_i2s0   DT_N_S_soc_S_peripheral_40000000_S_i2s_28000
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_IDX_0_VAL_ADDRESS   1073905664 /* 0x40028000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_irq   40
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_COMPAT_MATCHES_nordic_nrf_i2s   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_STATUS_disabled   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg   {163840 /* 0x28000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_0   163840
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts   {40 /* 0x28 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_0   40
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source   "PCLK32M_HFXO"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_STRING_TOKEN   PCLK32M_HFXO
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_STRING_UPPER_TOKEN   PCLK32M_HFXO
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_ENUM_TOKEN   PCLK32M_HFXO
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_ENUM_UPPER_TOKEN   PCLK32M_HFXO
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status   "disabled"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible   {"nordic,nrf-i2s"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_IDX_0   "nordic,nrf-i2s"
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_IDX_0_TOKEN   nordic_nrf_i2s
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_I2S
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_PATH   "/soc/peripheral@40000000/ipc@2a000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FULL_NAME   "ipc@2a000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_CHILD_IDX   9
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_ORD   60
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_ipc   DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000
 
#define DT_N_NODELABEL_ipc   DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_REG_IDX_0_VAL_ADDRESS   1073913856 /* 0x4002a000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_VAL_irq   42
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_COMPAT_MATCHES_nordic_nrf_ipc   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg   {172032 /* 0x2a000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_IDX_0   172032
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts   {42 /* 0x2a */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_IDX_0   42
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible   {"nordic,nrf-ipc"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_IDX_0   "nordic,nrf-ipc"
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_IDX_0_TOKEN   nordic_nrf_ipc
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_IPC
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_PATH   "/soc/peripheral@40000000/kmu@39000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FULL_NAME   "kmu@39000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_CHILD_IDX   11
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_ORD   61
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_kmu   DT_N_S_soc_S_peripheral_40000000_S_kmu_39000
 
#define DT_N_NODELABEL_kmu   DT_N_S_soc_S_peripheral_40000000_S_kmu_39000
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_IDX_0_VAL_ADDRESS   1073975296 /* 0x40039000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_irq   57
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_COMPAT_MATCHES_nordic_nrf_kmu   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg   {233472 /* 0x39000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_0   233472
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts   {57 /* 0x39 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_0   57
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible   {"nordic,nrf-kmu"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_IDX_0   "nordic,nrf-kmu"
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_IDX_0_TOKEN   nordic_nrf_kmu
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_KMU
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_PATH   "/soc/peripheral@40000000/pdm@26000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FULL_NAME   "pdm@26000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_CHILD_IDX   12
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_ORD   62
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_pdm   DT_N_S_soc_S_peripheral_40000000_S_pdm_26000
 
#define DT_N_NODELABEL_pdm0   DT_N_S_soc_S_peripheral_40000000_S_pdm_26000
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_IDX_0_VAL_ADDRESS   1073897472 /* 0x40026000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_irq   38
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_COMPAT_MATCHES_nordic_nrf_pdm   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_STATUS_disabled   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg   {155648 /* 0x26000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_0   155648
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts   {38 /* 0x26 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_0   38
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source   "PCLK32M_HFXO"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_STRING_TOKEN   PCLK32M_HFXO
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_STRING_UPPER_TOKEN   PCLK32M_HFXO
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_ENUM_TOKEN   PCLK32M_HFXO
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_ENUM_UPPER_TOKEN   PCLK32M_HFXO
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_queue_size   4
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_queue_size_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status   "disabled"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible   {"nordic,nrf-pdm"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_IDX_0   "nordic,nrf-pdm"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_IDX_0_TOKEN   nordic_nrf_pdm
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_PDM
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_PATH   "/soc/peripheral@40000000/power@5000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_FULL_NAME   "power@5000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_CHILD_IDX   35
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_ORD   63
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_power   DT_N_S_soc_S_peripheral_40000000_S_power_5000
 
#define DT_N_NODELABEL_power   DT_N_S_soc_S_peripheral_40000000_S_power_5000
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_IDX_0_VAL_ADDRESS   1073762304 /* 0x40005000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_irq   5
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_COMPAT_MATCHES_nordic_nrf_power   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg   {20480 /* 0x5000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_0   20480
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts   {5 /* 0x5 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_0   5
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible   {"nordic,nrf-power"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_IDX_0   "nordic,nrf-power"
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_IDX_0_TOKEN   nordic_nrf_power
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_POWER
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_PATH   "/soc/peripheral@40000000/pwm@21000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FULL_NAME   "pwm@21000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_CHILD_IDX   27
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_ORD   64
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_pwm   DT_N_S_soc_S_peripheral_40000000_S_pwm_21000
 
#define DT_N_NODELABEL_pwm0   DT_N_S_soc_S_peripheral_40000000_S_pwm_21000
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_IDX_0_VAL_ADDRESS   1073876992 /* 0x40021000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_irq   33
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_COMPAT_MATCHES_nordic_nrf_pwm   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_STATUS_disabled   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg   {135168 /* 0x21000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_0   135168
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_center_aligned   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_center_aligned_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch0_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch0_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch1_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch1_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch2_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch2_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch3_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch3_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status   "disabled"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible   {"nordic,nrf-pwm"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_IDX_0   "nordic,nrf-pwm"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_IDX_0_TOKEN   nordic_nrf_pwm
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_PWM
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts   {33 /* 0x21 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_0   33
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_PATH   "/soc/peripheral@40000000/pwm@22000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FULL_NAME   "pwm@22000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_CHILD_IDX   28
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_ORD   65
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_EXISTS   1
 
#define DT_N_INST_1_nordic_nrf_pwm   DT_N_S_soc_S_peripheral_40000000_S_pwm_22000
 
#define DT_N_NODELABEL_pwm1   DT_N_S_soc_S_peripheral_40000000_S_pwm_22000
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_IDX_0_VAL_ADDRESS   1073881088 /* 0x40022000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_irq   34
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_COMPAT_MATCHES_nordic_nrf_pwm   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_STATUS_disabled   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg   {139264 /* 0x22000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_0   139264
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_center_aligned   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_center_aligned_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch0_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch0_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch1_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch1_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch2_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch2_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch3_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch3_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status   "disabled"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible   {"nordic,nrf-pwm"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_IDX_0   "nordic,nrf-pwm"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_IDX_0_TOKEN   nordic_nrf_pwm
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_PWM
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts   {34 /* 0x22 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_0   34
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_PATH   "/soc/peripheral@40000000/pwm@23000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FULL_NAME   "pwm@23000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_CHILD_IDX   29
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_ORD   66
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_EXISTS   1
 
#define DT_N_INST_2_nordic_nrf_pwm   DT_N_S_soc_S_peripheral_40000000_S_pwm_23000
 
#define DT_N_NODELABEL_pwm2   DT_N_S_soc_S_peripheral_40000000_S_pwm_23000
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_IDX_0_VAL_ADDRESS   1073885184 /* 0x40023000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_irq   35
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_COMPAT_MATCHES_nordic_nrf_pwm   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_STATUS_disabled   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg   {143360 /* 0x23000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_0   143360
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_center_aligned   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_center_aligned_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch0_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch0_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch1_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch1_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch2_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch2_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch3_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch3_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status   "disabled"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible   {"nordic,nrf-pwm"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_IDX_0   "nordic,nrf-pwm"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_IDX_0_TOKEN   nordic_nrf_pwm
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_PWM
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts   {35 /* 0x23 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_0   35
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_PATH   "/soc/peripheral@40000000/pwm@24000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FULL_NAME   "pwm@24000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_CHILD_IDX   30
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_ORD   67
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_EXISTS   1
 
#define DT_N_INST_3_nordic_nrf_pwm   DT_N_S_soc_S_peripheral_40000000_S_pwm_24000
 
#define DT_N_NODELABEL_pwm3   DT_N_S_soc_S_peripheral_40000000_S_pwm_24000
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_IDX_0_VAL_ADDRESS   1073889280 /* 0x40024000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_irq   36
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_COMPAT_MATCHES_nordic_nrf_pwm   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_STATUS_disabled   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg   {147456 /* 0x24000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_0   147456
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_center_aligned   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_center_aligned_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch0_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch0_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch1_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch1_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch2_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch2_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch3_inverted   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch3_inverted_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status   "disabled"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible   {"nordic,nrf-pwm"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_IDX_0   "nordic,nrf-pwm"
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_IDX_0_TOKEN   nordic_nrf_pwm
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_PWM
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts   {36 /* 0x24 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_0   36
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_PATH   "/soc/peripheral@40000000/regulator@4000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FULL_NAME   "regulator@4000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_CHILD_IDX   13
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_ORD   68
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REQUIRES_ORDS    7, /* /soc/peripheral@40000000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_regulators   DT_N_S_soc_S_peripheral_40000000_S_regulator_4000
 
#define DT_N_NODELABEL_regulators   DT_N_S_soc_S_peripheral_40000000_S_regulator_4000
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_IDX_0_VAL_ADDRESS   1073758208 /* 0x40004000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_COMPAT_MATCHES_nordic_nrf_regulators   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg   {16384 /* 0x4000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_0   16384
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible   {"nordic,nrf-regulators"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_IDX_0   "nordic,nrf-regulators"
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_IDX_0_TOKEN   nordic_nrf_regulators
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_REGULATORS
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_PATH   "/soc/peripheral@40000000/rtc@14000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FULL_NAME   "rtc@14000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_CHILD_IDX   32
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_ORD   69
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_rtc   DT_N_S_soc_S_peripheral_40000000_S_rtc_14000
 
#define DT_N_NODELABEL_rtc0   DT_N_S_soc_S_peripheral_40000000_S_rtc_14000
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_IDX_0_VAL_ADDRESS   1073823744 /* 0x40014000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_irq   20
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_COMPAT_MATCHES_nordic_nrf_rtc   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg   {81920 /* 0x14000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_0   81920
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_cc_num   4
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_cc_num_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_ppi_wrap   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_ppi_wrap_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_fixed_top   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_fixed_top_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_clock_frequency   32768
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_clock_frequency_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts   {20 /* 0x14 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_0   20
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_prescaler   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_prescaler_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible   {"nordic,nrf-rtc"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_IDX_0   "nordic,nrf-rtc"
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_IDX_0_TOKEN   nordic_nrf_rtc
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_RTC
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_PATH   "/soc/peripheral@40000000/rtc@15000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FULL_NAME   "rtc@15000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_CHILD_IDX   33
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_ORD   70
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_EXISTS   1
 
#define DT_N_INST_1_nordic_nrf_rtc   DT_N_S_soc_S_peripheral_40000000_S_rtc_15000
 
#define DT_N_NODELABEL_rtc1   DT_N_S_soc_S_peripheral_40000000_S_rtc_15000
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_IDX_0_VAL_ADDRESS   1073827840 /* 0x40015000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_irq   21
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_COMPAT_MATCHES_nordic_nrf_rtc   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg   {86016 /* 0x15000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_0   86016
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_cc_num   4
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_cc_num_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_ppi_wrap   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_ppi_wrap_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_fixed_top   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_fixed_top_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_clock_frequency   32768
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_clock_frequency_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts   {21 /* 0x15 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_0   21
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_prescaler   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_prescaler_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible   {"nordic,nrf-rtc"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_IDX_0   "nordic,nrf-rtc"
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_IDX_0_TOKEN   nordic_nrf_rtc
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_RTC
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_PATH   "/soc/peripheral@40000000/spi@8000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FULL_NAME   "spi@8000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_CHILD_IDX   23
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_ORD   71
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_EXISTS   1
 
#define DT_N_INST_1_nordic_nrf_spim   DT_N_S_soc_S_peripheral_40000000_S_spi_8000
 
#define DT_N_NODELABEL_spi0   DT_N_S_soc_S_peripheral_40000000_S_spi_8000
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_IDX_0_VAL_ADDRESS   1073774592 /* 0x40008000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_irq   8
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_COMPAT_MATCHES_nordic_nrf_spim   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_STATUS_disabled   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_miso_pull_up   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_miso_pull_up_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_miso_pull_down   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_miso_pull_down_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_anomaly_58_workaround   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_anomaly_58_workaround_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_rx_delay_supported   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_rx_delay_supported_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg   {32768 /* 0x8000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_0   32768
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts   {8 /* 0x8 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_0   8
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_max_frequency   8000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_max_frequency_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_overrun_character   255
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_overrun_character_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status   "disabled"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible   {"nordic,nrf-spim"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_IDX_0   "nordic,nrf-spim"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_IDX_0_TOKEN   nordic_nrf_spim
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_SPIM
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_PATH   "/soc/peripheral@40000000/spi@9000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FULL_NAME   "spi@9000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_CHILD_IDX   24
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_ORD   72
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_EXISTS   1
 
#define DT_N_INST_2_nordic_nrf_spim   DT_N_S_soc_S_peripheral_40000000_S_spi_9000
 
#define DT_N_NODELABEL_spi1   DT_N_S_soc_S_peripheral_40000000_S_spi_9000
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_IDX_0_VAL_ADDRESS   1073778688 /* 0x40009000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_irq   9
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_COMPAT_MATCHES_nordic_nrf_spim   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_STATUS_disabled   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_miso_pull_up   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_miso_pull_up_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_miso_pull_down   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_miso_pull_down_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_anomaly_58_workaround   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_anomaly_58_workaround_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_rx_delay_supported   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_rx_delay_supported_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg   {36864 /* 0x9000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_0   36864
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts   {9 /* 0x9 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_0   9
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_max_frequency   8000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_max_frequency_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_overrun_character   255
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_overrun_character_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status   "disabled"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible   {"nordic,nrf-spim"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_IDX_0   "nordic,nrf-spim"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_IDX_0_TOKEN   nordic_nrf_spim
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_SPIM
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_PATH   "/soc/peripheral@40000000/spi@b000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FULL_NAME   "spi@b000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_CHILD_IDX   26
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_ORD   73
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_EXISTS   1
 
#define DT_N_INST_3_nordic_nrf_spim   DT_N_S_soc_S_peripheral_40000000_S_spi_b000
 
#define DT_N_NODELABEL_spi3   DT_N_S_soc_S_peripheral_40000000_S_spi_b000
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_IDX_0_VAL_ADDRESS   1073786880 /* 0x4000b000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_irq   11
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_COMPAT_MATCHES_nordic_nrf_spim   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_STATUS_disabled   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_up   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_up_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_down   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_down_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_anomaly_58_workaround   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_anomaly_58_workaround_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_rx_delay_supported   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_rx_delay_supported_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg   {45056 /* 0xb000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_0   45056
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts   {11 /* 0xb */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_0   11
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_max_frequency   8000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_max_frequency_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_overrun_character   255
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_overrun_character_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status   "disabled"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible   {"nordic,nrf-spim"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_IDX_0   "nordic,nrf-spim"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_IDX_0_TOKEN   nordic_nrf_spim
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_SPIM
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_PATH   "/soc/peripheral@40000000/timer@f000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FULL_NAME   "timer@f000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_CHILD_IDX   37
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_ORD   74
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_timer   DT_N_S_soc_S_peripheral_40000000_S_timer_f000
 
#define DT_N_NODELABEL_timer0   DT_N_S_soc_S_peripheral_40000000_S_timer_f000
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_IDX_0_VAL_ADDRESS   1073803264 /* 0x4000f000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_irq   15
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_COMPAT_MATCHES_nordic_nrf_timer   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg   {61440 /* 0xf000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_0   61440
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_cc_num   6
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_cc_num_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts   {15 /* 0xf */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_0   15
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_prescaler   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_prescaler_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible   {"nordic,nrf-timer"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_IDX_0   "nordic,nrf-timer"
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_IDX_0_TOKEN   nordic_nrf_timer
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_TIMER
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_PATH   "/soc/peripheral@40000000/timer@10000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FULL_NAME   "timer@10000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_CHILD_IDX   38
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_ORD   75
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_EXISTS   1
 
#define DT_N_INST_1_nordic_nrf_timer   DT_N_S_soc_S_peripheral_40000000_S_timer_10000
 
#define DT_N_NODELABEL_timer1   DT_N_S_soc_S_peripheral_40000000_S_timer_10000
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_IDX_0_VAL_ADDRESS   1073807360 /* 0x40010000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_irq   16
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_COMPAT_MATCHES_nordic_nrf_timer   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg   {65536 /* 0x10000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_0   65536
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_cc_num   6
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_cc_num_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts   {16 /* 0x10 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_0   16
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_prescaler   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_prescaler_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible   {"nordic,nrf-timer"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_IDX_0   "nordic,nrf-timer"
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_IDX_0_TOKEN   nordic_nrf_timer
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_TIMER
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_PATH   "/soc/peripheral@40000000/timer@11000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FULL_NAME   "timer@11000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_CHILD_IDX   39
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_ORD   76
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_EXISTS   1
 
#define DT_N_INST_2_nordic_nrf_timer   DT_N_S_soc_S_peripheral_40000000_S_timer_11000
 
#define DT_N_NODELABEL_timer2   DT_N_S_soc_S_peripheral_40000000_S_timer_11000
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_IDX_0_VAL_ADDRESS   1073811456 /* 0x40011000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_irq   17
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_COMPAT_MATCHES_nordic_nrf_timer   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg   {69632 /* 0x11000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_0   69632
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_cc_num   6
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_cc_num_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts   {17 /* 0x11 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_0   17
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_prescaler   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_prescaler_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible   {"nordic,nrf-timer"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_IDX_0   "nordic,nrf-timer"
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_IDX_0_TOKEN   nordic_nrf_timer
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_TIMER
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PATH   "/soc/peripheral@40000000/uart@8000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FULL_NAME   "uart@8000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_CHILD_IDX   15
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_ORD   77
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_uarte   DT_N_S_soc_S_peripheral_40000000_S_uart_8000
 
#define DT_N_NODELABEL_uart0   DT_N_S_soc_S_peripheral_40000000_S_uart_8000
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_IDX_0_VAL_ADDRESS   1073774592 /* 0x40008000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_irq   8
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_COMPAT_MATCHES_nordic_nrf_uarte   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NUM   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_0_TOKEN   default
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_0_UPPER_TOKEN   DEFAULT
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_default_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_default_IDX   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_default_IDX_0_PH   DT_N_S_pin_controller_S_uart0_default
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_1_TOKEN   sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_1_UPPER_TOKEN   SLEEP
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_sleep_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_sleep_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_sleep_IDX_0_PH   DT_N_S_pin_controller_S_uart0_sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg   {32768 /* 0x8000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_0   32768
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts   {8 /* 0x8 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_0   8
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_disable_rx   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_disable_rx_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_current_speed   115200
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_current_speed_ENUM_IDX   12
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_current_speed_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_rx_pull_up   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_rx_pull_up_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_cts_pull_up   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_cts_pull_up_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_hw_flow_control   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_hw_flow_control_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible   {"nordic,nrf-uarte"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_IDX_0   "nordic,nrf-uarte"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_IDX_0_TOKEN   nordic_nrf_uarte
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_UARTE
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_IDX_0   DT_N_S_pin_controller_S_uart0_default
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_IDX_0_PH   DT_N_S_pin_controller_S_uart0_default
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, pinctrl_0, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, pinctrl_0, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_IDX_0   DT_N_S_pin_controller_S_uart0_sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_IDX_0_PH   DT_N_S_pin_controller_S_uart0_sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, pinctrl_1, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, pinctrl_1, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names   {"default", "sleep"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_0   "default"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_0_TOKEN   default
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_0_UPPER_TOKEN   DEFAULT
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_1   "sleep"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_1_TOKEN   sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_1_UPPER_TOKEN   SLEEP
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_LEN   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_PATH   "/soc/peripheral@40000000/uart@9000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FULL_NAME   "uart@9000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_CHILD_IDX   16
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_ORD   78
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_EXISTS   1
 
#define DT_N_INST_1_nordic_nrf_uarte   DT_N_S_soc_S_peripheral_40000000_S_uart_9000
 
#define DT_N_NODELABEL_uart1   DT_N_S_soc_S_peripheral_40000000_S_uart_9000
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_IDX_0_VAL_ADDRESS   1073778688 /* 0x40009000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_irq   9
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_COMPAT_MATCHES_nordic_nrf_uarte   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_STATUS_disabled   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg   {36864 /* 0x9000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_0   36864
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts   {9 /* 0x9 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_0   9
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_disable_rx   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_disable_rx_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_rx_pull_up   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_rx_pull_up_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_cts_pull_up   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_cts_pull_up_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_hw_flow_control   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_hw_flow_control_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status   "disabled"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible   {"nordic,nrf-uarte"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_IDX_0   "nordic,nrf-uarte"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_IDX_0_TOKEN   nordic_nrf_uarte
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_UARTE
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PATH   "/soc/peripheral@40000000/uart@a000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FULL_NAME   "uart@a000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_CHILD_IDX   17
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_ORD   79
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_EXISTS   1
 
#define DT_N_INST_2_nordic_nrf_uarte   DT_N_S_soc_S_peripheral_40000000_S_uart_a000
 
#define DT_N_NODELABEL_uart2   DT_N_S_soc_S_peripheral_40000000_S_uart_a000
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_IDX_0_VAL_ADDRESS   1073782784 /* 0x4000a000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_irq   10
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_COMPAT_MATCHES_nordic_nrf_uarte   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_STATUS_disabled   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NUM   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_0_TOKEN   default
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_0_UPPER_TOKEN   DEFAULT
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_default_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_default_IDX   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_default_IDX_0_PH   DT_N_S_pin_controller_S_uart2_default
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_1_TOKEN   sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_1_UPPER_TOKEN   SLEEP
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_sleep_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_sleep_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_sleep_IDX_0_PH   DT_N_S_pin_controller_S_uart2_sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg   {40960 /* 0xa000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_0   40960
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts   {10 /* 0xa */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_0   10
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_disable_rx   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_disable_rx_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_rx_pull_up   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_rx_pull_up_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_cts_pull_up   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_cts_pull_up_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_hw_flow_control   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_hw_flow_control_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status   "disabled"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible   {"nordic,nrf-uarte"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_IDX_0   "nordic,nrf-uarte"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_IDX_0_TOKEN   nordic_nrf_uarte
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_UARTE
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_IDX_0   DT_N_S_pin_controller_S_uart2_default
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_IDX_0_PH   DT_N_S_pin_controller_S_uart2_default
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, pinctrl_0, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, pinctrl_0, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_IDX_0   DT_N_S_pin_controller_S_uart2_sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_IDX_0_PH   DT_N_S_pin_controller_S_uart2_sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, pinctrl_1, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, pinctrl_1, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names   {"default", "sleep"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_0   "default"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_0_TOKEN   default
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_0_UPPER_TOKEN   DEFAULT
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_1   "sleep"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_1_TOKEN   sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_1_UPPER_TOKEN   SLEEP
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_LEN   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_PATH   "/soc/peripheral@40000000/uart@b000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FULL_NAME   "uart@b000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_CHILD_IDX   18
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_ORD   80
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_EXISTS   1
 
#define DT_N_INST_3_nordic_nrf_uarte   DT_N_S_soc_S_peripheral_40000000_S_uart_b000
 
#define DT_N_NODELABEL_uart3   DT_N_S_soc_S_peripheral_40000000_S_uart_b000
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_IDX_0_VAL_ADDRESS   1073786880 /* 0x4000b000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_irq   11
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_COMPAT_MATCHES_nordic_nrf_uarte   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_STATUS_disabled   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg   {45056 /* 0xb000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_0   45056
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts   {11 /* 0xb */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_0   11
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_disable_rx   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_disable_rx_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_rx_pull_up   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_rx_pull_up_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_cts_pull_up   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_cts_pull_up_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_hw_flow_control   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_hw_flow_control_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status   "disabled"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_STRING_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_STRING_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_ENUM_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_ENUM_TOKEN   disabled
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_ENUM_UPPER_TOKEN   DISABLED
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible   {"nordic,nrf-uarte"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_IDX_0   "nordic,nrf-uarte"
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_IDX_0_TOKEN   nordic_nrf_uarte
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_UARTE
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_PATH   "/soc/peripheral@40000000/vmc@3a000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FULL_NAME   "vmc@3a000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_CHILD_IDX   14
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_ORD   81
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REQUIRES_ORDS    7, /* /soc/peripheral@40000000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_vmc   DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000
 
#define DT_N_NODELABEL_vmc   DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_IDX_0_VAL_ADDRESS   1073979392 /* 0x4003a000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_COMPAT_MATCHES_nordic_nrf_vmc   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg   {237568 /* 0x3a000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_0   237568
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible   {"nordic,nrf-vmc"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_IDX_0   "nordic,nrf-vmc"
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_IDX_0_TOKEN   nordic_nrf_vmc
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_VMC
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_PATH   "/soc/peripheral@40000000/watchdog@18000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FULL_NAME   "watchdog@18000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_CHILD_IDX   36
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_ORD   82
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_EXISTS   1
 
#define DT_N_ALIAS_watchdog0   DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000
 
#define DT_N_INST_0_nordic_nrf_wdt   DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000
 
#define DT_N_NODELABEL_wdt   DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000
 
#define DT_N_NODELABEL_wdt0   DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_IDX_0_VAL_ADDRESS   1073840128 /* 0x40018000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq   24
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_COMPAT_MATCHES_nordic_nrf_wdt   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg   {98304 /* 0x18000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_0   98304
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts   {24 /* 0x18 */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_0   24
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible   {"nordic,nrf-wdt"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_IDX_0   "nordic,nrf-wdt"
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_IDX_0_TOKEN   nordic_nrf_wdt
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_WDT
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_PATH   "/soc/peripheral@40000000/adc@e000/channel@0"
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FULL_NAME   "channel@0"
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_PARENT   DT_N_S_soc_S_peripheral_40000000_S_adc_e000
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_CHILD_IDX   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_ORD   83
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_REQUIRES_ORDS    8, /* /soc/peripheral@40000000/adc@e000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_REG_IDX_0_VAL_ADDRESS   0 /* 0x0 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg   {0 /* 0x0 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg_IDX_0   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, reg, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, reg, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain   "ADC_GAIN_1_5"
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_STRING_TOKEN   ADC_GAIN_1_5
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_STRING_UPPER_TOKEN   ADC_GAIN_1_5
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_ENUM_TOKEN   ADC_GAIN_1_5
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_ENUM_UPPER_TOKEN   ADC_GAIN_1_5
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference   "ADC_REF_INTERNAL"
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_STRING_TOKEN   ADC_REF_INTERNAL
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_STRING_UPPER_TOKEN   ADC_REF_INTERNAL
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_ENUM_IDX   4
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_ENUM_TOKEN   ADC_REF_INTERNAL
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_ENUM_UPPER_TOKEN   ADC_REF_INTERNAL
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_acquisition_time   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_acquisition_time_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_input_positive   4
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_input_positive_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_resolution   12
 
#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_resolution_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_PATH   "/soc/peripheral@40000000/flash-controller@39000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FULL_NAME   "flash-controller@39000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_CHILD_IDX   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_CHILD(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_ORD   84
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REQUIRES_ORDS    7, /* /soc/peripheral@40000000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_SUPPORTS_ORDS    85, /* /soc/peripheral@40000000/flash-controller@39000/flash@0 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf91_flash_controller   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000
 
#define DT_N_NODELABEL_flash_controller   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_IDX_0_VAL_ADDRESS   1073975296 /* 0x40039000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_COMPAT_MATCHES_nordic_nrf91_flash_controller   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_partial_erase   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_partial_erase_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg   {233472 /* 0x39000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_0   233472
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible   {"nordic,nrf91-flash-controller"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_IDX_0   "nordic,nrf91-flash-controller"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_IDX_0_TOKEN   nordic_nrf91_flash_controller
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF91_FLASH_CONTROLLER
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FULL_NAME   "flash@0"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_CHILD_IDX   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_ORD   85
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REQUIRES_ORDS    84, /* /soc/peripheral@40000000/flash-controller@39000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_SUPPORTS_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_EXISTS   1
 
#define DT_N_INST_0_soc_nv_flash   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0
 
#define DT_N_NODELABEL_flash0   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_ADDRESS   0 /* 0x0 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_SIZE   1048576 /* 0x100000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_COMPAT_MATCHES_soc_nv_flash   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_erase_block_size   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_erase_block_size_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_write_block_size   4
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_write_block_size_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible   {"soc-nv-flash"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0   "soc-nv-flash"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_TOKEN   soc_nv_flash
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_UPPER_TOKEN   SOC_NV_FLASH
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg   {0 /* 0x0 */, 1048576 /* 0x100000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1   1048576
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FULL_NAME   "partitions"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_CHILD_IDX   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_ORD   86
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_REQUIRES_ORDS    85, /* /soc/peripheral@40000000/flash-controller@39000/flash@0 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_SUPPORTS_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_EXISTS   1
 
#define DT_N_INST_0_fixed_partitions   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_REG_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_COMPAT_MATCHES_fixed_partitions   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@0"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FULL_NAME   "partition@0"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_CHILD_IDX   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_ORD   87
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REQUIRES_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_EXISTS   1
 
#define DT_N_NODELABEL_boot_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS   0 /* 0x0 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE   65536 /* 0x10000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARTITION_ID   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label   "mcuboot"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_TOKEN   mcuboot
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UPPER_TOKEN   MCUBOOT
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg   {0 /* 0x0 */, 65536 /* 0x10000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1   65536
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@10000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FULL_NAME   "partition@10000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_CHILD_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_ORD   88
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REQUIRES_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_EXISTS   1
 
#define DT_N_NODELABEL_slot0_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_ADDRESS   65536 /* 0x10000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_SIZE   262144 /* 0x40000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARTITION_ID   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label   "image-0"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_TOKEN   image_0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_UPPER_TOKEN   IMAGE_0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg   {65536 /* 0x10000 */, 262144 /* 0x40000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0   65536
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1   262144
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@50000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FULL_NAME   "partition@50000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_CHILD_IDX   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_ORD   89
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REQUIRES_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_EXISTS   1
 
#define DT_N_NODELABEL_slot0_ns_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_ADDRESS   327680 /* 0x50000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_SIZE   196608 /* 0x30000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARTITION_ID   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label   "image-0-nonsecure"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_TOKEN   image_0_nonsecure
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_UPPER_TOKEN   IMAGE_0_NONSECURE
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg   {327680 /* 0x50000 */, 196608 /* 0x30000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0   327680
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1   196608
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@80000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FULL_NAME   "partition@80000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_CHILD_IDX   3
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_ORD   90
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REQUIRES_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_EXISTS   1
 
#define DT_N_NODELABEL_slot1_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_ADDRESS   524288 /* 0x80000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_SIZE   262144 /* 0x40000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARTITION_ID   3
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label   "image-1"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_STRING_TOKEN   image_1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_STRING_UPPER_TOKEN   IMAGE_1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg   {524288 /* 0x80000 */, 262144 /* 0x40000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_0   524288
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_1   262144
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@c0000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FULL_NAME   "partition@c0000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_CHILD_IDX   4
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_ORD   91
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REQUIRES_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_EXISTS   1
 
#define DT_N_NODELABEL_slot1_ns_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_VAL_ADDRESS   786432 /* 0xc0000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_VAL_SIZE   196608 /* 0x30000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PARTITION_ID   4
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label   "image-1-nonsecure"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_STRING_TOKEN   image_1_nonsecure
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_STRING_UPPER_TOKEN   IMAGE_1_NONSECURE
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_read_only   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_read_only_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg   {786432 /* 0xc0000 */, 196608 /* 0x30000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_0   786432
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_1   196608
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@f0000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FULL_NAME   "partition@f0000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_CHILD_IDX   5
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_ORD   92
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REQUIRES_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_EXISTS   1
 
#define DT_N_NODELABEL_scratch_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_VAL_ADDRESS   983040 /* 0xf0000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_VAL_SIZE   40960 /* 0xa000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PARTITION_ID   5
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label   "image-scratch"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_STRING_TOKEN   image_scratch
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_STRING_UPPER_TOKEN   IMAGE_SCRATCH
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_read_only   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_read_only_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg   {983040 /* 0xf0000 */, 40960 /* 0xa000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_0   983040
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_1   40960
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@fa000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FULL_NAME   "partition@fa000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_CHILD_IDX   6
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_ORD   93
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REQUIRES_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_EXISTS   1
 
#define DT_N_NODELABEL_storage_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_VAL_ADDRESS   1024000 /* 0xfa000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_VAL_SIZE   24576 /* 0x6000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PARTITION_ID   6
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label   "storage"
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_STRING_TOKEN   storage
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_STRING_UPPER_TOKEN   STORAGE
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_read_only   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_read_only_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg   {1024000 /* 0xfa000 */, 24576 /* 0x6000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_0   1024000
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_1   24576
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PATH   "/soc/peripheral@40000000/spi@a000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FULL_NAME   "spi@a000"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PARENT   DT_N_S_soc_S_peripheral_40000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_CHILD_IDX   25
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_CHILD(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_CHILD_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_ORD   94
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REQUIRES_ORDS
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_SUPPORTS_ORDS    95, /* /soc/peripheral@40000000/spi@a000/ls0xx@0 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_EXISTS   1
 
#define DT_N_INST_0_nordic_nrf_spim   DT_N_S_soc_S_peripheral_40000000_S_spi_a000
 
#define DT_N_NODELABEL_spi2   DT_N_S_soc_S_peripheral_40000000_S_spi_a000
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_IDX_0_VAL_ADDRESS   1073782784 /* 0x4000a000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_irq   10
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_irq_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_priority   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_priority_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_COMPAT_MATCHES_nordic_nrf_spim   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NUM   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_0_TOKEN   default
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_0_UPPER_TOKEN   DEFAULT
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_default_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_default_IDX   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_default_IDX_0_PH   DT_N_S_pin_controller_S_spi2_default
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_1_TOKEN   sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_1_UPPER_TOKEN   SLEEP
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_sleep_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_sleep_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_sleep_IDX_0_PH   DT_N_S_pin_controller_S_spi2_sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_miso_pull_up   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_miso_pull_up_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_miso_pull_down   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_miso_pull_down_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_anomaly_58_workaround   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_anomaly_58_workaround_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_rx_delay_supported   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_rx_delay_supported_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg   {40960 /* 0xa000 */, 4096 /* 0x1000 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_0   40960
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_1   4096
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts   {10 /* 0xa */, 1 /* 0x1 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_0   10
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_1   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_max_frequency   8000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_max_frequency_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_overrun_character   255
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_overrun_character_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_pin   28
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_pin_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_flags   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_flags_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_VAL_pin   20
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_VAL_pin_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_VAL_flags   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_VAL_flags_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_LEN   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status   "okay"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_STRING_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_STRING_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_ENUM_IDX   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_ENUM_TOKEN   okay
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_ENUM_UPPER_TOKEN   OKAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible   {"nordic,nrf-spim"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_IDX_0   "nordic,nrf-spim"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_IDX_0_TOKEN   nordic_nrf_spim
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_SPIM
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_IDX_0   DT_N_S_pin_controller_S_spi2_default
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_IDX_0_PH   DT_N_S_pin_controller_S_spi2_default
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, pinctrl_0, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, pinctrl_0, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_IDX_0   DT_N_S_pin_controller_S_spi2_sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_IDX_0_PH   DT_N_S_pin_controller_S_spi2_sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, pinctrl_1, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, pinctrl_1, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names   {"default", "sleep"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_0   "default"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_0_TOKEN   default
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_0_UPPER_TOKEN   DEFAULT
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_1   "sleep"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_1_TOKEN   sleep
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_1_UPPER_TOKEN   SLEEP
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_1_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_LEN   2
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_PATH   "/soc/peripheral@40000000/spi@a000/ls0xx@0"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FULL_NAME   "ls0xx@0"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_PARENT   DT_N_S_soc_S_peripheral_40000000_S_spi_a000
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_CHILD_IDX   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FOREACH_CHILD(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FOREACH_CHILD_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FOREACH_CHILD_STATUS_OKAY(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_ORD   95
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_REQUIRES_ORDS    94, /* /soc/peripheral@40000000/spi@a000 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_SUPPORTS_ORDS   /* nothing */
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_EXISTS   1
 
#define DT_N_INST_0_sharp_ls0xx   DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0
 
#define DT_N_NODELABEL_ls0xx   DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_BUS_spi   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_BUS   DT_N_S_soc_S_peripheral_40000000_S_spi_a000
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_REG_NUM   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_REG_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_REG_IDX_0_VAL_ADDRESS   0 /* 0x0 */
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_RANGES_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FOREACH_RANGE(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_IRQ_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_COMPAT_MATCHES_sharp_ls0xx   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_STATUS_okay   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_PINCTRL_NUM   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg   {0 /* 0x0 */}
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg_IDX_0   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, reg, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, reg, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_spi_max_frequency   2000000
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_spi_max_frequency_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_duplex   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_duplex_ENUM_IDX   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_duplex_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_frame_format   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_frame_format_ENUM_IDX   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_frame_format_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible   {"sharp,ls0xx"}
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_IDX_0   "sharp,ls0xx"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_IDX_0_TOKEN   sharp_ls0xx
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_IDX_0_UPPER_TOKEN   SHARP_LS0XX
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_IDX_0_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_FOREACH_PROP_ELEM(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, compatible, 0)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, compatible, 0, __VA_ARGS__)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_LEN   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label   "DISPLAY"
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label_STRING_TOKEN   DISPLAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label_STRING_UPPER_TOKEN   DISPLAY
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label_FOREACH_PROP_ELEM(fn)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label_FOREACH_PROP_ELEM_VARGS(fn, ...)
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_wakeup_source   0
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_wakeup_source_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_height   68
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_height_EXISTS   1
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_width   160
 
#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_width_EXISTS   1
 
#define DT_CHOSEN_zephyr_flash_controller   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000
 
#define DT_CHOSEN_zephyr_flash_controller_EXISTS   1
 
#define DT_CHOSEN_zephyr_entropy   DT_N_S_cryptocell_sw
 
#define DT_CHOSEN_zephyr_entropy_EXISTS   1
 
#define DT_CHOSEN_zephyr_console   DT_N_S_soc_S_peripheral_40000000_S_uart_8000
 
#define DT_CHOSEN_zephyr_console_EXISTS   1
 
#define DT_CHOSEN_zephyr_shell_uart   DT_N_S_soc_S_peripheral_40000000_S_uart_8000
 
#define DT_CHOSEN_zephyr_shell_uart_EXISTS   1
 
#define DT_CHOSEN_zephyr_uart_mcumgr   DT_N_S_soc_S_peripheral_40000000_S_uart_8000
 
#define DT_CHOSEN_zephyr_uart_mcumgr_EXISTS   1
 
#define DT_CHOSEN_zephyr_display   DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0
 
#define DT_CHOSEN_zephyr_display_EXISTS   1
 
#define DT_CHOSEN_zephyr_flash   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0
 
#define DT_CHOSEN_zephyr_flash_EXISTS   1
 
#define DT_CHOSEN_zephyr_sram   DT_N_S_reserved_memory_S_image_ns_20020000
 
#define DT_CHOSEN_zephyr_sram_EXISTS   1
 
#define DT_CHOSEN_zephyr_code_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000
 
#define DT_CHOSEN_zephyr_code_partition_EXISTS   1
 
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0
 
#define DT_COMPAT_fixed_partitions_LABEL_mcuboot_EXISTS   1
 
#define DT_COMPAT_fixed_partitions_LABEL_image_0   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000
 
#define DT_COMPAT_fixed_partitions_LABEL_image_0_EXISTS   1
 
#define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000
 
#define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure_EXISTS   1
 
#define DT_COMPAT_fixed_partitions_LABEL_image_1   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000
 
#define DT_COMPAT_fixed_partitions_LABEL_image_1_EXISTS   1
 
#define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000
 
#define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure_EXISTS   1
 
#define DT_COMPAT_fixed_partitions_LABEL_image_scratch   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000
 
#define DT_COMPAT_fixed_partitions_LABEL_image_scratch_EXISTS   1
 
#define DT_COMPAT_fixed_partitions_LABEL_storage   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000
 
#define DT_COMPAT_fixed_partitions_LABEL_storage_EXISTS   1
 
#define DT_COMPAT_HAS_OKAY_nordic_ltewatch_nrf9160   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf9160_sica   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf9160   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf91   1
 
#define DT_COMPAT_HAS_OKAY_simple_bus   1
 
#define DT_COMPAT_HAS_OKAY_arm_v8m_nvic   1
 
#define DT_COMPAT_HAS_OKAY_mmio_sram   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf91_flash_controller   1
 
#define DT_COMPAT_HAS_OKAY_soc_nv_flash   1
 
#define DT_COMPAT_HAS_OKAY_fixed_partitions   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_saadc   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_dppic   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_egu   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_ipc   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_kmu   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_regulators   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_vmc   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_uarte   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_twim   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_spim   1
 
#define DT_COMPAT_HAS_OKAY_sharp_ls0xx   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpio   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_rtc   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_clock   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_power   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_wdt   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_timer   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpiote   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_pinctrl   1
 
#define DT_COMPAT_HAS_OKAY_zephyr_bt_hci_entropy   1
 
#define DT_COMPAT_HAS_OKAY_arm_cortex_m33f   1
 
#define DT_COMPAT_HAS_OKAY_arm_armv8m_mpu   1
 
#define DT_COMPAT_HAS_OKAY_nordic_nrf_cc310_sw   1
 
#define DT_COMPAT_HAS_OKAY_gpio_leds   1
 
#define DT_COMPAT_HAS_OKAY_gpio_keys   1
 
#define DT_N_INST_nordic_ltewatch_nrf9160_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf9160_sica_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf9160_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf91_NUM_OKAY   1
 
#define DT_N_INST_simple_bus_NUM_OKAY   1
 
#define DT_N_INST_arm_v8m_nvic_NUM_OKAY   1
 
#define DT_N_INST_mmio_sram_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf91_flash_controller_NUM_OKAY   1
 
#define DT_N_INST_soc_nv_flash_NUM_OKAY   1
 
#define DT_N_INST_fixed_partitions_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_saadc_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_dppic_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_egu_NUM_OKAY   6
 
#define DT_N_INST_nordic_nrf_ipc_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_kmu_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_regulators_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_vmc_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_uarte_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_twim_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_spim_NUM_OKAY   1
 
#define DT_N_INST_sharp_ls0xx_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_gpio_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_rtc_NUM_OKAY   2
 
#define DT_N_INST_nordic_nrf_clock_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_power_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_wdt_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_timer_NUM_OKAY   3
 
#define DT_N_INST_nordic_nrf_gpiote_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_pinctrl_NUM_OKAY   1
 
#define DT_N_INST_zephyr_bt_hci_entropy_NUM_OKAY   1
 
#define DT_N_INST_arm_cortex_m33f_NUM_OKAY   1
 
#define DT_N_INST_arm_armv8m_mpu_NUM_OKAY   1
 
#define DT_N_INST_nordic_nrf_cc310_sw_NUM_OKAY   1
 
#define DT_N_INST_gpio_leds_NUM_OKAY   1
 
#define DT_N_INST_gpio_keys_NUM_OKAY   1
 
#define DT_FOREACH_OKAY_nordic_ltewatch_nrf9160(fn)   fn(DT_N)
 
#define DT_FOREACH_OKAY_VARGS_nordic_ltewatch_nrf9160(fn, ...)   fn(DT_N, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_ltewatch_nrf9160(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_ltewatch_nrf9160(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf9160_sica(fn)   fn(DT_N_S_soc)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf9160_sica(fn, ...)   fn(DT_N_S_soc, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf9160_sica(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf9160_sica(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf9160(fn)   fn(DT_N_S_soc)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf9160(fn, ...)   fn(DT_N_S_soc, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf9160(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf9160(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf91(fn)   fn(DT_N_S_soc)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf91(fn, ...)   fn(DT_N_S_soc, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf91(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf91(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_simple_bus(fn)   fn(DT_N_S_soc)
 
#define DT_FOREACH_OKAY_VARGS_simple_bus(fn, ...)   fn(DT_N_S_soc, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_simple_bus(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_simple_bus(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_arm_v8m_nvic(fn)   fn(DT_N_S_soc_S_interrupt_controller_e000e100)
 
#define DT_FOREACH_OKAY_VARGS_arm_v8m_nvic(fn, ...)   fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_arm_v8m_nvic(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_arm_v8m_nvic(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_mmio_sram(fn)   fn(DT_N_S_soc_S_memory_20000000)
 
#define DT_FOREACH_OKAY_VARGS_mmio_sram(fn, ...)   fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_mmio_sram(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_mmio_sram(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf91_flash_controller(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf91_flash_controller(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf91_flash_controller(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf91_flash_controller(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_soc_nv_flash(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0)
 
#define DT_FOREACH_OKAY_VARGS_soc_nv_flash(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_soc_nv_flash(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_soc_nv_flash(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_fixed_partitions(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions)
 
#define DT_FOREACH_OKAY_VARGS_fixed_partitions(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_fixed_partitions(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_fixed_partitions(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_saadc(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_saadc(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_saadc(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_saadc(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_dppic(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_dppic(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_dppic(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_dppic(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_egu(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_egu(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_egu(fn)   fn(0) fn(1) fn(2) fn(3) fn(4) fn(5)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_egu(fn, ...)   fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) fn(3, __VA_ARGS__) fn(4, __VA_ARGS__) fn(5, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_ipc(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_ipc(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_ipc(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ipc(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_kmu(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_kmu(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_kmu(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_kmu(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_regulators(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_regulators(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_regulators(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_regulators(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_vmc(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_vmc(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_vmc(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_vmc(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_uarte(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_uarte(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_uarte(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_uarte(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_twim(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_twim(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_twim(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_twim(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_spim(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_spim(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_spim(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_spim(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_sharp_ls0xx(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0)
 
#define DT_FOREACH_OKAY_VARGS_sharp_ls0xx(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_sharp_ls0xx(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_sharp_ls0xx(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_gpio(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpio(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpio(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpio(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_rtc(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_rtc(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_rtc(fn)   fn(0) fn(1)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_rtc(fn, ...)   fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_clock(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_clock(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_clock(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_clock(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_power(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_power(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_power(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_power(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_wdt(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_wdt(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_wdt(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_wdt(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_timer(fn)   fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_timer(fn, ...)   fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_timer(fn)   fn(0) fn(1) fn(2)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_timer(fn, ...)   fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_gpiote(fn)   fn(DT_N_S_soc_S_gpiote_40031000)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpiote(fn, ...)   fn(DT_N_S_soc_S_gpiote_40031000, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_gpiote(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpiote(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_pinctrl(fn)   fn(DT_N_S_pin_controller)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_pinctrl(fn, ...)   fn(DT_N_S_pin_controller, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_pinctrl(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_pinctrl(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_zephyr_bt_hci_entropy(fn)   fn(DT_N_S_entropy_bt_hci)
 
#define DT_FOREACH_OKAY_VARGS_zephyr_bt_hci_entropy(fn, ...)   fn(DT_N_S_entropy_bt_hci, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_zephyr_bt_hci_entropy(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_zephyr_bt_hci_entropy(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_arm_cortex_m33f(fn)   fn(DT_N_S_cpus_S_cpu_0)
 
#define DT_FOREACH_OKAY_VARGS_arm_cortex_m33f(fn, ...)   fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_arm_cortex_m33f(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_arm_cortex_m33f(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_arm_armv8m_mpu(fn)   fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)
 
#define DT_FOREACH_OKAY_VARGS_arm_armv8m_mpu(fn, ...)   fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_arm_armv8m_mpu(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_arm_armv8m_mpu(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_nordic_nrf_cc310_sw(fn)   fn(DT_N_S_cryptocell_sw)
 
#define DT_FOREACH_OKAY_VARGS_nordic_nrf_cc310_sw(fn, ...)   fn(DT_N_S_cryptocell_sw, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_nordic_nrf_cc310_sw(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_cc310_sw(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_gpio_leds(fn)   fn(DT_N_S_leds)
 
#define DT_FOREACH_OKAY_VARGS_gpio_leds(fn, ...)   fn(DT_N_S_leds, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_gpio_leds(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_gpio_leds(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_gpio_keys(fn)   fn(DT_N_S_buttons)
 
#define DT_FOREACH_OKAY_VARGS_gpio_keys(fn, ...)   fn(DT_N_S_buttons, __VA_ARGS__)
 
#define DT_FOREACH_OKAY_INST_gpio_keys(fn)   fn(0)
 
#define DT_FOREACH_OKAY_INST_VARGS_gpio_keys(fn, ...)   fn(0, __VA_ARGS__)
 
#define DT_COMPAT_sharp_ls0xx_BUS_spi   1
 

Macro Definition Documentation

◆ DT_CHOSEN_zephyr_code_partition

#define DT_CHOSEN_zephyr_code_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000

◆ DT_CHOSEN_zephyr_code_partition_EXISTS

#define DT_CHOSEN_zephyr_code_partition_EXISTS   1

◆ DT_CHOSEN_zephyr_console

#define DT_CHOSEN_zephyr_console   DT_N_S_soc_S_peripheral_40000000_S_uart_8000

◆ DT_CHOSEN_zephyr_console_EXISTS

#define DT_CHOSEN_zephyr_console_EXISTS   1

◆ DT_CHOSEN_zephyr_display

#define DT_CHOSEN_zephyr_display   DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0

◆ DT_CHOSEN_zephyr_display_EXISTS

#define DT_CHOSEN_zephyr_display_EXISTS   1

◆ DT_CHOSEN_zephyr_entropy

#define DT_CHOSEN_zephyr_entropy   DT_N_S_cryptocell_sw

◆ DT_CHOSEN_zephyr_entropy_EXISTS

#define DT_CHOSEN_zephyr_entropy_EXISTS   1

◆ DT_CHOSEN_zephyr_flash

#define DT_CHOSEN_zephyr_flash   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0

◆ DT_CHOSEN_zephyr_flash_controller

#define DT_CHOSEN_zephyr_flash_controller   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000

◆ DT_CHOSEN_zephyr_flash_controller_EXISTS

#define DT_CHOSEN_zephyr_flash_controller_EXISTS   1

◆ DT_CHOSEN_zephyr_flash_EXISTS

#define DT_CHOSEN_zephyr_flash_EXISTS   1

◆ DT_CHOSEN_zephyr_shell_uart

#define DT_CHOSEN_zephyr_shell_uart   DT_N_S_soc_S_peripheral_40000000_S_uart_8000

◆ DT_CHOSEN_zephyr_shell_uart_EXISTS

#define DT_CHOSEN_zephyr_shell_uart_EXISTS   1

◆ DT_CHOSEN_zephyr_sram

#define DT_CHOSEN_zephyr_sram   DT_N_S_reserved_memory_S_image_ns_20020000

◆ DT_CHOSEN_zephyr_sram_EXISTS

#define DT_CHOSEN_zephyr_sram_EXISTS   1

◆ DT_CHOSEN_zephyr_uart_mcumgr

#define DT_CHOSEN_zephyr_uart_mcumgr   DT_N_S_soc_S_peripheral_40000000_S_uart_8000

◆ DT_CHOSEN_zephyr_uart_mcumgr_EXISTS

#define DT_CHOSEN_zephyr_uart_mcumgr_EXISTS   1

◆ DT_COMPAT_fixed_partitions_LABEL_image_0

#define DT_COMPAT_fixed_partitions_LABEL_image_0   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000

◆ DT_COMPAT_fixed_partitions_LABEL_image_0_EXISTS

#define DT_COMPAT_fixed_partitions_LABEL_image_0_EXISTS   1

◆ DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure

#define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000

◆ DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure_EXISTS

#define DT_COMPAT_fixed_partitions_LABEL_image_0_nonsecure_EXISTS   1

◆ DT_COMPAT_fixed_partitions_LABEL_image_1

#define DT_COMPAT_fixed_partitions_LABEL_image_1   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000

◆ DT_COMPAT_fixed_partitions_LABEL_image_1_EXISTS

#define DT_COMPAT_fixed_partitions_LABEL_image_1_EXISTS   1

◆ DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure

#define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000

◆ DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure_EXISTS

#define DT_COMPAT_fixed_partitions_LABEL_image_1_nonsecure_EXISTS   1

◆ DT_COMPAT_fixed_partitions_LABEL_image_scratch

#define DT_COMPAT_fixed_partitions_LABEL_image_scratch   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000

◆ DT_COMPAT_fixed_partitions_LABEL_image_scratch_EXISTS

#define DT_COMPAT_fixed_partitions_LABEL_image_scratch_EXISTS   1

◆ DT_COMPAT_fixed_partitions_LABEL_mcuboot

#define DT_COMPAT_fixed_partitions_LABEL_mcuboot   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0

◆ DT_COMPAT_fixed_partitions_LABEL_mcuboot_EXISTS

#define DT_COMPAT_fixed_partitions_LABEL_mcuboot_EXISTS   1

◆ DT_COMPAT_fixed_partitions_LABEL_storage

#define DT_COMPAT_fixed_partitions_LABEL_storage   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000

◆ DT_COMPAT_fixed_partitions_LABEL_storage_EXISTS

#define DT_COMPAT_fixed_partitions_LABEL_storage_EXISTS   1

◆ DT_COMPAT_HAS_OKAY_arm_armv8m_mpu

#define DT_COMPAT_HAS_OKAY_arm_armv8m_mpu   1

◆ DT_COMPAT_HAS_OKAY_arm_cortex_m33f

#define DT_COMPAT_HAS_OKAY_arm_cortex_m33f   1

◆ DT_COMPAT_HAS_OKAY_arm_v8m_nvic

#define DT_COMPAT_HAS_OKAY_arm_v8m_nvic   1

◆ DT_COMPAT_HAS_OKAY_fixed_partitions

#define DT_COMPAT_HAS_OKAY_fixed_partitions   1

◆ DT_COMPAT_HAS_OKAY_gpio_keys

#define DT_COMPAT_HAS_OKAY_gpio_keys   1

◆ DT_COMPAT_HAS_OKAY_gpio_leds

#define DT_COMPAT_HAS_OKAY_gpio_leds   1

◆ DT_COMPAT_HAS_OKAY_mmio_sram

#define DT_COMPAT_HAS_OKAY_mmio_sram   1

◆ DT_COMPAT_HAS_OKAY_nordic_ltewatch_nrf9160

#define DT_COMPAT_HAS_OKAY_nordic_ltewatch_nrf9160   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf91

#define DT_COMPAT_HAS_OKAY_nordic_nrf91   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf9160

#define DT_COMPAT_HAS_OKAY_nordic_nrf9160   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf9160_sica

#define DT_COMPAT_HAS_OKAY_nordic_nrf9160_sica   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf91_flash_controller

#define DT_COMPAT_HAS_OKAY_nordic_nrf91_flash_controller   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_cc310_sw

#define DT_COMPAT_HAS_OKAY_nordic_nrf_cc310_sw   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_clock

#define DT_COMPAT_HAS_OKAY_nordic_nrf_clock   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_dppic

#define DT_COMPAT_HAS_OKAY_nordic_nrf_dppic   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_egu

#define DT_COMPAT_HAS_OKAY_nordic_nrf_egu   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_gpio

#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpio   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_gpiote

#define DT_COMPAT_HAS_OKAY_nordic_nrf_gpiote   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_ipc

#define DT_COMPAT_HAS_OKAY_nordic_nrf_ipc   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_kmu

#define DT_COMPAT_HAS_OKAY_nordic_nrf_kmu   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_pinctrl

#define DT_COMPAT_HAS_OKAY_nordic_nrf_pinctrl   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_power

#define DT_COMPAT_HAS_OKAY_nordic_nrf_power   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_regulators

#define DT_COMPAT_HAS_OKAY_nordic_nrf_regulators   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_rtc

#define DT_COMPAT_HAS_OKAY_nordic_nrf_rtc   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_saadc

#define DT_COMPAT_HAS_OKAY_nordic_nrf_saadc   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_spim

#define DT_COMPAT_HAS_OKAY_nordic_nrf_spim   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_timer

#define DT_COMPAT_HAS_OKAY_nordic_nrf_timer   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_twim

#define DT_COMPAT_HAS_OKAY_nordic_nrf_twim   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_uarte

#define DT_COMPAT_HAS_OKAY_nordic_nrf_uarte   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_vmc

#define DT_COMPAT_HAS_OKAY_nordic_nrf_vmc   1

◆ DT_COMPAT_HAS_OKAY_nordic_nrf_wdt

#define DT_COMPAT_HAS_OKAY_nordic_nrf_wdt   1

◆ DT_COMPAT_HAS_OKAY_sharp_ls0xx

#define DT_COMPAT_HAS_OKAY_sharp_ls0xx   1

◆ DT_COMPAT_HAS_OKAY_simple_bus

#define DT_COMPAT_HAS_OKAY_simple_bus   1

◆ DT_COMPAT_HAS_OKAY_soc_nv_flash

#define DT_COMPAT_HAS_OKAY_soc_nv_flash   1

◆ DT_COMPAT_HAS_OKAY_zephyr_bt_hci_entropy

#define DT_COMPAT_HAS_OKAY_zephyr_bt_hci_entropy   1

◆ DT_COMPAT_sharp_ls0xx_BUS_spi

#define DT_COMPAT_sharp_ls0xx_BUS_spi   1

◆ DT_FOREACH_OKAY_arm_armv8m_mpu

#define DT_FOREACH_OKAY_arm_armv8m_mpu (   fn)    fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)

◆ DT_FOREACH_OKAY_arm_cortex_m33f

#define DT_FOREACH_OKAY_arm_cortex_m33f (   fn)    fn(DT_N_S_cpus_S_cpu_0)

◆ DT_FOREACH_OKAY_arm_v8m_nvic

#define DT_FOREACH_OKAY_arm_v8m_nvic (   fn)    fn(DT_N_S_soc_S_interrupt_controller_e000e100)

◆ DT_FOREACH_OKAY_fixed_partitions

#define DT_FOREACH_OKAY_fixed_partitions (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions)

◆ DT_FOREACH_OKAY_gpio_keys

#define DT_FOREACH_OKAY_gpio_keys (   fn)    fn(DT_N_S_buttons)

◆ DT_FOREACH_OKAY_gpio_leds

#define DT_FOREACH_OKAY_gpio_leds (   fn)    fn(DT_N_S_leds)

◆ DT_FOREACH_OKAY_INST_arm_armv8m_mpu

#define DT_FOREACH_OKAY_INST_arm_armv8m_mpu (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_arm_cortex_m33f

#define DT_FOREACH_OKAY_INST_arm_cortex_m33f (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_arm_v8m_nvic

#define DT_FOREACH_OKAY_INST_arm_v8m_nvic (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_fixed_partitions

#define DT_FOREACH_OKAY_INST_fixed_partitions (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_gpio_keys

#define DT_FOREACH_OKAY_INST_gpio_keys (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_gpio_leds

#define DT_FOREACH_OKAY_INST_gpio_leds (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_mmio_sram

#define DT_FOREACH_OKAY_INST_mmio_sram (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_ltewatch_nrf9160

#define DT_FOREACH_OKAY_INST_nordic_ltewatch_nrf9160 (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf91

#define DT_FOREACH_OKAY_INST_nordic_nrf91 (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf9160

#define DT_FOREACH_OKAY_INST_nordic_nrf9160 (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf9160_sica

#define DT_FOREACH_OKAY_INST_nordic_nrf9160_sica (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf91_flash_controller

#define DT_FOREACH_OKAY_INST_nordic_nrf91_flash_controller (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_cc310_sw

#define DT_FOREACH_OKAY_INST_nordic_nrf_cc310_sw (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_clock

#define DT_FOREACH_OKAY_INST_nordic_nrf_clock (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_dppic

#define DT_FOREACH_OKAY_INST_nordic_nrf_dppic (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_egu

#define DT_FOREACH_OKAY_INST_nordic_nrf_egu (   fn)    fn(0) fn(1) fn(2) fn(3) fn(4) fn(5)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_gpio

#define DT_FOREACH_OKAY_INST_nordic_nrf_gpio (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_gpiote

#define DT_FOREACH_OKAY_INST_nordic_nrf_gpiote (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_ipc

#define DT_FOREACH_OKAY_INST_nordic_nrf_ipc (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_kmu

#define DT_FOREACH_OKAY_INST_nordic_nrf_kmu (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_pinctrl

#define DT_FOREACH_OKAY_INST_nordic_nrf_pinctrl (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_power

#define DT_FOREACH_OKAY_INST_nordic_nrf_power (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_regulators

#define DT_FOREACH_OKAY_INST_nordic_nrf_regulators (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_rtc

#define DT_FOREACH_OKAY_INST_nordic_nrf_rtc (   fn)    fn(0) fn(1)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_saadc

#define DT_FOREACH_OKAY_INST_nordic_nrf_saadc (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_spim

#define DT_FOREACH_OKAY_INST_nordic_nrf_spim (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_timer

#define DT_FOREACH_OKAY_INST_nordic_nrf_timer (   fn)    fn(0) fn(1) fn(2)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_twim

#define DT_FOREACH_OKAY_INST_nordic_nrf_twim (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_uarte

#define DT_FOREACH_OKAY_INST_nordic_nrf_uarte (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_vmc

#define DT_FOREACH_OKAY_INST_nordic_nrf_vmc (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_nordic_nrf_wdt

#define DT_FOREACH_OKAY_INST_nordic_nrf_wdt (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_sharp_ls0xx

#define DT_FOREACH_OKAY_INST_sharp_ls0xx (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_simple_bus

#define DT_FOREACH_OKAY_INST_simple_bus (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_soc_nv_flash

#define DT_FOREACH_OKAY_INST_soc_nv_flash (   fn)    fn(0)

◆ DT_FOREACH_OKAY_INST_VARGS_arm_armv8m_mpu

#define DT_FOREACH_OKAY_INST_VARGS_arm_armv8m_mpu (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_arm_cortex_m33f

#define DT_FOREACH_OKAY_INST_VARGS_arm_cortex_m33f (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_arm_v8m_nvic

#define DT_FOREACH_OKAY_INST_VARGS_arm_v8m_nvic (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_fixed_partitions

#define DT_FOREACH_OKAY_INST_VARGS_fixed_partitions (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_gpio_keys

#define DT_FOREACH_OKAY_INST_VARGS_gpio_keys (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_gpio_leds

#define DT_FOREACH_OKAY_INST_VARGS_gpio_leds (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_mmio_sram

#define DT_FOREACH_OKAY_INST_VARGS_mmio_sram (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_ltewatch_nrf9160

#define DT_FOREACH_OKAY_INST_VARGS_nordic_ltewatch_nrf9160 (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf91

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf91 (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf9160

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf9160 (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf9160_sica

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf9160_sica (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf91_flash_controller

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf91_flash_controller (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_cc310_sw

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_cc310_sw (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_clock

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_clock (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_dppic

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_dppic (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_egu

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_egu (   fn,
  ... 
)    fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__) fn(3, __VA_ARGS__) fn(4, __VA_ARGS__) fn(5, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpio

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpio (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpiote

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_gpiote (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ipc

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_ipc (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_kmu

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_kmu (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_pinctrl

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_pinctrl (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_power

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_power (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_regulators

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_regulators (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_rtc

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_rtc (   fn,
  ... 
)    fn(0, __VA_ARGS__) fn(1, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_saadc

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_saadc (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_spim

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_spim (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_timer

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_timer (   fn,
  ... 
)    fn(0, __VA_ARGS__) fn(1, __VA_ARGS__) fn(2, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_twim

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_twim (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_uarte

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_uarte (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_vmc

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_vmc (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_wdt

#define DT_FOREACH_OKAY_INST_VARGS_nordic_nrf_wdt (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_sharp_ls0xx

#define DT_FOREACH_OKAY_INST_VARGS_sharp_ls0xx (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_simple_bus

#define DT_FOREACH_OKAY_INST_VARGS_simple_bus (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_soc_nv_flash

#define DT_FOREACH_OKAY_INST_VARGS_soc_nv_flash (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_VARGS_zephyr_bt_hci_entropy

#define DT_FOREACH_OKAY_INST_VARGS_zephyr_bt_hci_entropy (   fn,
  ... 
)    fn(0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_INST_zephyr_bt_hci_entropy

#define DT_FOREACH_OKAY_INST_zephyr_bt_hci_entropy (   fn)    fn(0)

◆ DT_FOREACH_OKAY_mmio_sram

#define DT_FOREACH_OKAY_mmio_sram (   fn)    fn(DT_N_S_soc_S_memory_20000000)

◆ DT_FOREACH_OKAY_nordic_ltewatch_nrf9160

#define DT_FOREACH_OKAY_nordic_ltewatch_nrf9160 (   fn)    fn(DT_N)

◆ DT_FOREACH_OKAY_nordic_nrf91

#define DT_FOREACH_OKAY_nordic_nrf91 (   fn)    fn(DT_N_S_soc)

◆ DT_FOREACH_OKAY_nordic_nrf9160

#define DT_FOREACH_OKAY_nordic_nrf9160 (   fn)    fn(DT_N_S_soc)

◆ DT_FOREACH_OKAY_nordic_nrf9160_sica

#define DT_FOREACH_OKAY_nordic_nrf9160_sica (   fn)    fn(DT_N_S_soc)

◆ DT_FOREACH_OKAY_nordic_nrf91_flash_controller

#define DT_FOREACH_OKAY_nordic_nrf91_flash_controller (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000)

◆ DT_FOREACH_OKAY_nordic_nrf_cc310_sw

#define DT_FOREACH_OKAY_nordic_nrf_cc310_sw (   fn)    fn(DT_N_S_cryptocell_sw)

◆ DT_FOREACH_OKAY_nordic_nrf_clock

#define DT_FOREACH_OKAY_nordic_nrf_clock (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000)

◆ DT_FOREACH_OKAY_nordic_nrf_dppic

#define DT_FOREACH_OKAY_nordic_nrf_dppic (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000)

◆ DT_FOREACH_OKAY_nordic_nrf_egu

#define DT_FOREACH_OKAY_nordic_nrf_egu (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000)

◆ DT_FOREACH_OKAY_nordic_nrf_gpio

#define DT_FOREACH_OKAY_nordic_nrf_gpio (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500)

◆ DT_FOREACH_OKAY_nordic_nrf_gpiote

#define DT_FOREACH_OKAY_nordic_nrf_gpiote (   fn)    fn(DT_N_S_soc_S_gpiote_40031000)

◆ DT_FOREACH_OKAY_nordic_nrf_ipc

#define DT_FOREACH_OKAY_nordic_nrf_ipc (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000)

◆ DT_FOREACH_OKAY_nordic_nrf_kmu

#define DT_FOREACH_OKAY_nordic_nrf_kmu (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000)

◆ DT_FOREACH_OKAY_nordic_nrf_pinctrl

#define DT_FOREACH_OKAY_nordic_nrf_pinctrl (   fn)    fn(DT_N_S_pin_controller)

◆ DT_FOREACH_OKAY_nordic_nrf_power

#define DT_FOREACH_OKAY_nordic_nrf_power (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000)

◆ DT_FOREACH_OKAY_nordic_nrf_regulators

#define DT_FOREACH_OKAY_nordic_nrf_regulators (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000)

◆ DT_FOREACH_OKAY_nordic_nrf_rtc

#define DT_FOREACH_OKAY_nordic_nrf_rtc (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000)

◆ DT_FOREACH_OKAY_nordic_nrf_saadc

#define DT_FOREACH_OKAY_nordic_nrf_saadc (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000)

◆ DT_FOREACH_OKAY_nordic_nrf_spim

#define DT_FOREACH_OKAY_nordic_nrf_spim (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000)

◆ DT_FOREACH_OKAY_nordic_nrf_timer

#define DT_FOREACH_OKAY_nordic_nrf_timer (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000)

◆ DT_FOREACH_OKAY_nordic_nrf_twim

#define DT_FOREACH_OKAY_nordic_nrf_twim (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000)

◆ DT_FOREACH_OKAY_nordic_nrf_uarte

#define DT_FOREACH_OKAY_nordic_nrf_uarte (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000)

◆ DT_FOREACH_OKAY_nordic_nrf_vmc

#define DT_FOREACH_OKAY_nordic_nrf_vmc (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000)

◆ DT_FOREACH_OKAY_nordic_nrf_wdt

#define DT_FOREACH_OKAY_nordic_nrf_wdt (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000)

◆ DT_FOREACH_OKAY_sharp_ls0xx

#define DT_FOREACH_OKAY_sharp_ls0xx (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0)

◆ DT_FOREACH_OKAY_simple_bus

#define DT_FOREACH_OKAY_simple_bus (   fn)    fn(DT_N_S_soc)

◆ DT_FOREACH_OKAY_soc_nv_flash

#define DT_FOREACH_OKAY_soc_nv_flash (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0)

◆ DT_FOREACH_OKAY_VARGS_arm_armv8m_mpu

#define DT_FOREACH_OKAY_VARGS_arm_armv8m_mpu (   fn,
  ... 
)    fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_arm_cortex_m33f

#define DT_FOREACH_OKAY_VARGS_arm_cortex_m33f (   fn,
  ... 
)    fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_arm_v8m_nvic

#define DT_FOREACH_OKAY_VARGS_arm_v8m_nvic (   fn,
  ... 
)    fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_fixed_partitions

#define DT_FOREACH_OKAY_VARGS_fixed_partitions (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_gpio_keys

#define DT_FOREACH_OKAY_VARGS_gpio_keys (   fn,
  ... 
)    fn(DT_N_S_buttons, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_gpio_leds

#define DT_FOREACH_OKAY_VARGS_gpio_leds (   fn,
  ... 
)    fn(DT_N_S_leds, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_mmio_sram

#define DT_FOREACH_OKAY_VARGS_mmio_sram (   fn,
  ... 
)    fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_ltewatch_nrf9160

#define DT_FOREACH_OKAY_VARGS_nordic_ltewatch_nrf9160 (   fn,
  ... 
)    fn(DT_N, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf91

#define DT_FOREACH_OKAY_VARGS_nordic_nrf91 (   fn,
  ... 
)    fn(DT_N_S_soc, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf9160

#define DT_FOREACH_OKAY_VARGS_nordic_nrf9160 (   fn,
  ... 
)    fn(DT_N_S_soc, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf9160_sica

#define DT_FOREACH_OKAY_VARGS_nordic_nrf9160_sica (   fn,
  ... 
)    fn(DT_N_S_soc, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf91_flash_controller

#define DT_FOREACH_OKAY_VARGS_nordic_nrf91_flash_controller (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_cc310_sw

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_cc310_sw (   fn,
  ... 
)    fn(DT_N_S_cryptocell_sw, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_clock

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_clock (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_dppic

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_dppic (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_egu

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_egu (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_gpio

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpio (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_gpiote

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_gpiote (   fn,
  ... 
)    fn(DT_N_S_soc_S_gpiote_40031000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_ipc

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_ipc (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_kmu

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_kmu (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_pinctrl

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_pinctrl (   fn,
  ... 
)    fn(DT_N_S_pin_controller, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_power

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_power (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_regulators

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_regulators (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_rtc

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_rtc (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_saadc

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_saadc (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_spim

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_spim (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_timer

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_timer (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_twim

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_twim (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_uarte

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_uarte (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_vmc

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_vmc (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_nordic_nrf_wdt

#define DT_FOREACH_OKAY_VARGS_nordic_nrf_wdt (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_sharp_ls0xx

#define DT_FOREACH_OKAY_VARGS_sharp_ls0xx (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_simple_bus

#define DT_FOREACH_OKAY_VARGS_simple_bus (   fn,
  ... 
)    fn(DT_N_S_soc, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_soc_nv_flash

#define DT_FOREACH_OKAY_VARGS_soc_nv_flash (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)

◆ DT_FOREACH_OKAY_VARGS_zephyr_bt_hci_entropy

#define DT_FOREACH_OKAY_VARGS_zephyr_bt_hci_entropy (   fn,
  ... 
)    fn(DT_N_S_entropy_bt_hci, __VA_ARGS__)

◆ DT_FOREACH_OKAY_zephyr_bt_hci_entropy

#define DT_FOREACH_OKAY_zephyr_bt_hci_entropy (   fn)    fn(DT_N_S_entropy_bt_hci)

◆ DT_N_ALIAS_bootloader_led0

#define DT_N_ALIAS_bootloader_led0   DT_N_S_leds_S_led_0

◆ DT_N_ALIAS_bt0

#define DT_N_ALIAS_bt0   DT_N_S_buttons_S_button_0

◆ DT_N_ALIAS_bt1

#define DT_N_ALIAS_bt1   DT_N_S_buttons_S_button_1

◆ DT_N_ALIAS_bt2

#define DT_N_ALIAS_bt2   DT_N_S_buttons_S_button_2

◆ DT_N_ALIAS_led0

#define DT_N_ALIAS_led0   DT_N_S_leds_S_led_0

◆ DT_N_ALIAS_led1

#define DT_N_ALIAS_led1   DT_N_S_leds_S_led_1

◆ DT_N_ALIAS_led2

#define DT_N_ALIAS_led2   DT_N_S_leds_S_led_2

◆ DT_N_ALIAS_mcuboot_button0

#define DT_N_ALIAS_mcuboot_button0   DT_N_S_buttons_S_button_0

◆ DT_N_ALIAS_mcuboot_led0

#define DT_N_ALIAS_mcuboot_led0   DT_N_S_leds_S_led_0

◆ DT_N_ALIAS_motord3com

#define DT_N_ALIAS_motord3com   DT_N_S_leds_S_led_1

◆ DT_N_ALIAS_motord3m1

#define DT_N_ALIAS_motord3m1   DT_N_S_leds_S_led_0

◆ DT_N_ALIAS_motord3m2

#define DT_N_ALIAS_motord3m2   DT_N_S_leds_S_led_2

◆ DT_N_ALIAS_watchdog0

#define DT_N_ALIAS_watchdog0   DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000

◆ DT_N_COMPAT_MATCHES_nordic_ltewatch_nrf9160

#define DT_N_COMPAT_MATCHES_nordic_ltewatch_nrf9160   1

◆ DT_N_EXISTS

#define DT_N_EXISTS   1

◆ DT_N_FOREACH_CHILD

#define DT_N_FOREACH_CHILD (   fn)    fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_cryptocell_sw) fn(DT_N_S_leds) fn(DT_N_S_buttons) fn(DT_N_S_reserved_memory) fn(DT_N_S_zephyr_user)

◆ DT_N_FOREACH_CHILD_STATUS_OKAY

#define DT_N_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_pin_controller) fn(DT_N_S_entropy_bt_hci) fn(DT_N_S_cpus) fn(DT_N_S_cryptocell_sw) fn(DT_N_S_leds) fn(DT_N_S_buttons) fn(DT_N_S_reserved_memory) fn(DT_N_S_zephyr_user)

◆ DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cryptocell_sw, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__)

◆ DT_N_FOREACH_CHILD_VARGS

#define DT_N_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_pin_controller, __VA_ARGS__) fn(DT_N_S_entropy_bt_hci, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cryptocell_sw, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_buttons, __VA_ARGS__) fn(DT_N_S_reserved_memory, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__)

◆ DT_N_FOREACH_RANGE

#define DT_N_FOREACH_RANGE (   fn)

◆ DT_N_FULL_NAME

#define DT_N_FULL_NAME   "/"

◆ DT_N_INST_0_arm_armv8m_mpu

#define DT_N_INST_0_arm_armv8m_mpu   DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90

◆ DT_N_INST_0_arm_armv8m_systick

#define DT_N_INST_0_arm_armv8m_systick   DT_N_S_soc_S_timer_e000e010

◆ DT_N_INST_0_arm_cortex_m33f

#define DT_N_INST_0_arm_cortex_m33f   DT_N_S_cpus_S_cpu_0

◆ DT_N_INST_0_arm_v8m_nvic

#define DT_N_INST_0_arm_v8m_nvic   DT_N_S_soc_S_interrupt_controller_e000e100

◆ DT_N_INST_0_fixed_partitions

#define DT_N_INST_0_fixed_partitions   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions

◆ DT_N_INST_0_gpio_keys

#define DT_N_INST_0_gpio_keys   DT_N_S_buttons

◆ DT_N_INST_0_gpio_leds

#define DT_N_INST_0_gpio_leds   DT_N_S_leds

◆ DT_N_INST_0_mmio_sram

#define DT_N_INST_0_mmio_sram   DT_N_S_soc_S_memory_20000000

◆ DT_N_INST_0_nordic_ltewatch_nrf9160

#define DT_N_INST_0_nordic_ltewatch_nrf9160   DT_N

◆ DT_N_INST_0_nordic_nrf91

#define DT_N_INST_0_nordic_nrf91   DT_N_S_soc

◆ DT_N_INST_0_nordic_nrf9160

#define DT_N_INST_0_nordic_nrf9160   DT_N_S_soc

◆ DT_N_INST_0_nordic_nrf9160_sica

#define DT_N_INST_0_nordic_nrf9160_sica   DT_N_S_soc

◆ DT_N_INST_0_nordic_nrf91_flash_controller

#define DT_N_INST_0_nordic_nrf91_flash_controller   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000

◆ DT_N_INST_0_nordic_nrf_cc310_sw

#define DT_N_INST_0_nordic_nrf_cc310_sw   DT_N_S_cryptocell_sw

◆ DT_N_INST_0_nordic_nrf_clock

#define DT_N_INST_0_nordic_nrf_clock   DT_N_S_soc_S_peripheral_40000000_S_clock_5000

◆ DT_N_INST_0_nordic_nrf_dppic

#define DT_N_INST_0_nordic_nrf_dppic   DT_N_S_soc_S_peripheral_40000000_S_dppic_17000

◆ DT_N_INST_0_nordic_nrf_egu

#define DT_N_INST_0_nordic_nrf_egu   DT_N_S_soc_S_peripheral_40000000_S_egu_1b000

◆ DT_N_INST_0_nordic_nrf_gpio

#define DT_N_INST_0_nordic_nrf_gpio   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_INST_0_nordic_nrf_gpiote

#define DT_N_INST_0_nordic_nrf_gpiote   DT_N_S_soc_S_gpiote_40031000

◆ DT_N_INST_0_nordic_nrf_i2s

#define DT_N_INST_0_nordic_nrf_i2s   DT_N_S_soc_S_peripheral_40000000_S_i2s_28000

◆ DT_N_INST_0_nordic_nrf_ipc

#define DT_N_INST_0_nordic_nrf_ipc   DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000

◆ DT_N_INST_0_nordic_nrf_kmu

#define DT_N_INST_0_nordic_nrf_kmu   DT_N_S_soc_S_peripheral_40000000_S_kmu_39000

◆ DT_N_INST_0_nordic_nrf_pdm

#define DT_N_INST_0_nordic_nrf_pdm   DT_N_S_soc_S_peripheral_40000000_S_pdm_26000

◆ DT_N_INST_0_nordic_nrf_pinctrl

#define DT_N_INST_0_nordic_nrf_pinctrl   DT_N_S_pin_controller

◆ DT_N_INST_0_nordic_nrf_power

#define DT_N_INST_0_nordic_nrf_power   DT_N_S_soc_S_peripheral_40000000_S_power_5000

◆ DT_N_INST_0_nordic_nrf_pwm

#define DT_N_INST_0_nordic_nrf_pwm   DT_N_S_soc_S_peripheral_40000000_S_pwm_21000

◆ DT_N_INST_0_nordic_nrf_regulators

#define DT_N_INST_0_nordic_nrf_regulators   DT_N_S_soc_S_peripheral_40000000_S_regulator_4000

◆ DT_N_INST_0_nordic_nrf_rtc

#define DT_N_INST_0_nordic_nrf_rtc   DT_N_S_soc_S_peripheral_40000000_S_rtc_14000

◆ DT_N_INST_0_nordic_nrf_saadc

#define DT_N_INST_0_nordic_nrf_saadc   DT_N_S_soc_S_peripheral_40000000_S_adc_e000

◆ DT_N_INST_0_nordic_nrf_spim

#define DT_N_INST_0_nordic_nrf_spim   DT_N_S_soc_S_peripheral_40000000_S_spi_a000

◆ DT_N_INST_0_nordic_nrf_timer

#define DT_N_INST_0_nordic_nrf_timer   DT_N_S_soc_S_peripheral_40000000_S_timer_f000

◆ DT_N_INST_0_nordic_nrf_twim

#define DT_N_INST_0_nordic_nrf_twim   DT_N_S_soc_S_peripheral_40000000_S_i2c_9000

◆ DT_N_INST_0_nordic_nrf_uarte

#define DT_N_INST_0_nordic_nrf_uarte   DT_N_S_soc_S_peripheral_40000000_S_uart_8000

◆ DT_N_INST_0_nordic_nrf_vmc

#define DT_N_INST_0_nordic_nrf_vmc   DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000

◆ DT_N_INST_0_nordic_nrf_wdt

#define DT_N_INST_0_nordic_nrf_wdt   DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000

◆ DT_N_INST_0_sharp_ls0xx

#define DT_N_INST_0_sharp_ls0xx   DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0

◆ DT_N_INST_0_simple_bus

#define DT_N_INST_0_simple_bus   DT_N_S_soc

◆ DT_N_INST_0_soc_nv_flash

#define DT_N_INST_0_soc_nv_flash   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0

◆ DT_N_INST_0_zephyr_bt_hci_entropy

#define DT_N_INST_0_zephyr_bt_hci_entropy   DT_N_S_entropy_bt_hci

◆ DT_N_INST_1_nordic_nrf_egu

#define DT_N_INST_1_nordic_nrf_egu   DT_N_S_soc_S_peripheral_40000000_S_egu_1c000

◆ DT_N_INST_1_nordic_nrf_pwm

#define DT_N_INST_1_nordic_nrf_pwm   DT_N_S_soc_S_peripheral_40000000_S_pwm_22000

◆ DT_N_INST_1_nordic_nrf_rtc

#define DT_N_INST_1_nordic_nrf_rtc   DT_N_S_soc_S_peripheral_40000000_S_rtc_15000

◆ DT_N_INST_1_nordic_nrf_spim

#define DT_N_INST_1_nordic_nrf_spim   DT_N_S_soc_S_peripheral_40000000_S_spi_8000

◆ DT_N_INST_1_nordic_nrf_timer

#define DT_N_INST_1_nordic_nrf_timer   DT_N_S_soc_S_peripheral_40000000_S_timer_10000

◆ DT_N_INST_1_nordic_nrf_twim

#define DT_N_INST_1_nordic_nrf_twim   DT_N_S_soc_S_peripheral_40000000_S_i2c_8000

◆ DT_N_INST_1_nordic_nrf_uarte

#define DT_N_INST_1_nordic_nrf_uarte   DT_N_S_soc_S_peripheral_40000000_S_uart_9000

◆ DT_N_INST_2_nordic_nrf_egu

#define DT_N_INST_2_nordic_nrf_egu   DT_N_S_soc_S_peripheral_40000000_S_egu_1d000

◆ DT_N_INST_2_nordic_nrf_pwm

#define DT_N_INST_2_nordic_nrf_pwm   DT_N_S_soc_S_peripheral_40000000_S_pwm_23000

◆ DT_N_INST_2_nordic_nrf_spim

#define DT_N_INST_2_nordic_nrf_spim   DT_N_S_soc_S_peripheral_40000000_S_spi_9000

◆ DT_N_INST_2_nordic_nrf_timer

#define DT_N_INST_2_nordic_nrf_timer   DT_N_S_soc_S_peripheral_40000000_S_timer_11000

◆ DT_N_INST_2_nordic_nrf_twim

#define DT_N_INST_2_nordic_nrf_twim   DT_N_S_soc_S_peripheral_40000000_S_i2c_a000

◆ DT_N_INST_2_nordic_nrf_uarte

#define DT_N_INST_2_nordic_nrf_uarte   DT_N_S_soc_S_peripheral_40000000_S_uart_a000

◆ DT_N_INST_3_nordic_nrf_egu

#define DT_N_INST_3_nordic_nrf_egu   DT_N_S_soc_S_peripheral_40000000_S_egu_1e000

◆ DT_N_INST_3_nordic_nrf_pwm

#define DT_N_INST_3_nordic_nrf_pwm   DT_N_S_soc_S_peripheral_40000000_S_pwm_24000

◆ DT_N_INST_3_nordic_nrf_spim

#define DT_N_INST_3_nordic_nrf_spim   DT_N_S_soc_S_peripheral_40000000_S_spi_b000

◆ DT_N_INST_3_nordic_nrf_twim

#define DT_N_INST_3_nordic_nrf_twim   DT_N_S_soc_S_peripheral_40000000_S_i2c_b000

◆ DT_N_INST_3_nordic_nrf_uarte

#define DT_N_INST_3_nordic_nrf_uarte   DT_N_S_soc_S_peripheral_40000000_S_uart_b000

◆ DT_N_INST_4_nordic_nrf_egu

#define DT_N_INST_4_nordic_nrf_egu   DT_N_S_soc_S_peripheral_40000000_S_egu_1f000

◆ DT_N_INST_5_nordic_nrf_egu

#define DT_N_INST_5_nordic_nrf_egu   DT_N_S_soc_S_peripheral_40000000_S_egu_20000

◆ DT_N_INST_arm_armv8m_mpu_NUM_OKAY

#define DT_N_INST_arm_armv8m_mpu_NUM_OKAY   1

◆ DT_N_INST_arm_cortex_m33f_NUM_OKAY

#define DT_N_INST_arm_cortex_m33f_NUM_OKAY   1

◆ DT_N_INST_arm_v8m_nvic_NUM_OKAY

#define DT_N_INST_arm_v8m_nvic_NUM_OKAY   1

◆ DT_N_INST_fixed_partitions_NUM_OKAY

#define DT_N_INST_fixed_partitions_NUM_OKAY   1

◆ DT_N_INST_gpio_keys_NUM_OKAY

#define DT_N_INST_gpio_keys_NUM_OKAY   1

◆ DT_N_INST_gpio_leds_NUM_OKAY

#define DT_N_INST_gpio_leds_NUM_OKAY   1

◆ DT_N_INST_mmio_sram_NUM_OKAY

#define DT_N_INST_mmio_sram_NUM_OKAY   1

◆ DT_N_INST_nordic_ltewatch_nrf9160_NUM_OKAY

#define DT_N_INST_nordic_ltewatch_nrf9160_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf9160_NUM_OKAY

#define DT_N_INST_nordic_nrf9160_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf9160_sica_NUM_OKAY

#define DT_N_INST_nordic_nrf9160_sica_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf91_flash_controller_NUM_OKAY

#define DT_N_INST_nordic_nrf91_flash_controller_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf91_NUM_OKAY

#define DT_N_INST_nordic_nrf91_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_cc310_sw_NUM_OKAY

#define DT_N_INST_nordic_nrf_cc310_sw_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_clock_NUM_OKAY

#define DT_N_INST_nordic_nrf_clock_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_dppic_NUM_OKAY

#define DT_N_INST_nordic_nrf_dppic_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_egu_NUM_OKAY

#define DT_N_INST_nordic_nrf_egu_NUM_OKAY   6

◆ DT_N_INST_nordic_nrf_gpio_NUM_OKAY

#define DT_N_INST_nordic_nrf_gpio_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_gpiote_NUM_OKAY

#define DT_N_INST_nordic_nrf_gpiote_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_ipc_NUM_OKAY

#define DT_N_INST_nordic_nrf_ipc_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_kmu_NUM_OKAY

#define DT_N_INST_nordic_nrf_kmu_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_pinctrl_NUM_OKAY

#define DT_N_INST_nordic_nrf_pinctrl_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_power_NUM_OKAY

#define DT_N_INST_nordic_nrf_power_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_regulators_NUM_OKAY

#define DT_N_INST_nordic_nrf_regulators_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_rtc_NUM_OKAY

#define DT_N_INST_nordic_nrf_rtc_NUM_OKAY   2

◆ DT_N_INST_nordic_nrf_saadc_NUM_OKAY

#define DT_N_INST_nordic_nrf_saadc_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_spim_NUM_OKAY

#define DT_N_INST_nordic_nrf_spim_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_timer_NUM_OKAY

#define DT_N_INST_nordic_nrf_timer_NUM_OKAY   3

◆ DT_N_INST_nordic_nrf_twim_NUM_OKAY

#define DT_N_INST_nordic_nrf_twim_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_uarte_NUM_OKAY

#define DT_N_INST_nordic_nrf_uarte_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_vmc_NUM_OKAY

#define DT_N_INST_nordic_nrf_vmc_NUM_OKAY   1

◆ DT_N_INST_nordic_nrf_wdt_NUM_OKAY

#define DT_N_INST_nordic_nrf_wdt_NUM_OKAY   1

◆ DT_N_INST_sharp_ls0xx_NUM_OKAY

#define DT_N_INST_sharp_ls0xx_NUM_OKAY   1

◆ DT_N_INST_simple_bus_NUM_OKAY

#define DT_N_INST_simple_bus_NUM_OKAY   1

◆ DT_N_INST_soc_nv_flash_NUM_OKAY

#define DT_N_INST_soc_nv_flash_NUM_OKAY   1

◆ DT_N_INST_zephyr_bt_hci_entropy_NUM_OKAY

#define DT_N_INST_zephyr_bt_hci_entropy_NUM_OKAY   1

◆ DT_N_IRQ_NUM

#define DT_N_IRQ_NUM   0

◆ DT_N_NODELABEL_adc

#define DT_N_NODELABEL_adc   DT_N_S_soc_S_peripheral_40000000_S_adc_e000

◆ DT_N_NODELABEL_boot_partition

#define DT_N_NODELABEL_boot_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0

◆ DT_N_NODELABEL_button0

#define DT_N_NODELABEL_button0   DT_N_S_buttons_S_button_0

◆ DT_N_NODELABEL_button1

#define DT_N_NODELABEL_button1   DT_N_S_buttons_S_button_1

◆ DT_N_NODELABEL_button2

#define DT_N_NODELABEL_button2   DT_N_S_buttons_S_button_2

◆ DT_N_NODELABEL_clock

#define DT_N_NODELABEL_clock   DT_N_S_soc_S_peripheral_40000000_S_clock_5000

◆ DT_N_NODELABEL_cryptocell_sw

#define DT_N_NODELABEL_cryptocell_sw   DT_N_S_cryptocell_sw

◆ DT_N_NODELABEL_dppic

#define DT_N_NODELABEL_dppic   DT_N_S_soc_S_peripheral_40000000_S_dppic_17000

◆ DT_N_NODELABEL_egu0

#define DT_N_NODELABEL_egu0   DT_N_S_soc_S_peripheral_40000000_S_egu_1b000

◆ DT_N_NODELABEL_egu1

#define DT_N_NODELABEL_egu1   DT_N_S_soc_S_peripheral_40000000_S_egu_1c000

◆ DT_N_NODELABEL_egu2

#define DT_N_NODELABEL_egu2   DT_N_S_soc_S_peripheral_40000000_S_egu_1d000

◆ DT_N_NODELABEL_egu3

#define DT_N_NODELABEL_egu3   DT_N_S_soc_S_peripheral_40000000_S_egu_1e000

◆ DT_N_NODELABEL_egu4

#define DT_N_NODELABEL_egu4   DT_N_S_soc_S_peripheral_40000000_S_egu_1f000

◆ DT_N_NODELABEL_egu5

#define DT_N_NODELABEL_egu5   DT_N_S_soc_S_peripheral_40000000_S_egu_20000

◆ DT_N_NODELABEL_flash0

#define DT_N_NODELABEL_flash0   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0

◆ DT_N_NODELABEL_flash_controller

#define DT_N_NODELABEL_flash_controller   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000

◆ DT_N_NODELABEL_gpio0

#define DT_N_NODELABEL_gpio0   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_NODELABEL_gpiote

#define DT_N_NODELABEL_gpiote   DT_N_S_soc_S_gpiote_40031000

◆ DT_N_NODELABEL_i2c0

#define DT_N_NODELABEL_i2c0   DT_N_S_soc_S_peripheral_40000000_S_i2c_8000

◆ DT_N_NODELABEL_i2c1

#define DT_N_NODELABEL_i2c1   DT_N_S_soc_S_peripheral_40000000_S_i2c_9000

◆ DT_N_NODELABEL_i2c1_default

#define DT_N_NODELABEL_i2c1_default   DT_N_S_pin_controller_S_i2c1_default

◆ DT_N_NODELABEL_i2c1_sleep

#define DT_N_NODELABEL_i2c1_sleep   DT_N_S_pin_controller_S_i2c1_sleep

◆ DT_N_NODELABEL_i2c2

#define DT_N_NODELABEL_i2c2   DT_N_S_soc_S_peripheral_40000000_S_i2c_a000

◆ DT_N_NODELABEL_i2c3

#define DT_N_NODELABEL_i2c3   DT_N_S_soc_S_peripheral_40000000_S_i2c_b000

◆ DT_N_NODELABEL_i2s0

#define DT_N_NODELABEL_i2s0   DT_N_S_soc_S_peripheral_40000000_S_i2s_28000

◆ DT_N_NODELABEL_ipc

#define DT_N_NODELABEL_ipc   DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000

◆ DT_N_NODELABEL_kmu

#define DT_N_NODELABEL_kmu   DT_N_S_soc_S_peripheral_40000000_S_kmu_39000

◆ DT_N_NODELABEL_led0

#define DT_N_NODELABEL_led0   DT_N_S_leds_S_led_0

◆ DT_N_NODELABEL_led1

#define DT_N_NODELABEL_led1   DT_N_S_leds_S_led_1

◆ DT_N_NODELABEL_led2

#define DT_N_NODELABEL_led2   DT_N_S_leds_S_led_2

◆ DT_N_NODELABEL_ls0xx

#define DT_N_NODELABEL_ls0xx   DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0

◆ DT_N_NODELABEL_mpu

#define DT_N_NODELABEL_mpu   DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90

◆ DT_N_NODELABEL_nvic

#define DT_N_NODELABEL_nvic   DT_N_S_soc_S_interrupt_controller_e000e100

◆ DT_N_NODELABEL_pdm0

#define DT_N_NODELABEL_pdm0   DT_N_S_soc_S_peripheral_40000000_S_pdm_26000

◆ DT_N_NODELABEL_pinctrl

#define DT_N_NODELABEL_pinctrl   DT_N_S_pin_controller

◆ DT_N_NODELABEL_power

#define DT_N_NODELABEL_power   DT_N_S_soc_S_peripheral_40000000_S_power_5000

◆ DT_N_NODELABEL_pwm0

#define DT_N_NODELABEL_pwm0   DT_N_S_soc_S_peripheral_40000000_S_pwm_21000

◆ DT_N_NODELABEL_pwm1

#define DT_N_NODELABEL_pwm1   DT_N_S_soc_S_peripheral_40000000_S_pwm_22000

◆ DT_N_NODELABEL_pwm2

#define DT_N_NODELABEL_pwm2   DT_N_S_soc_S_peripheral_40000000_S_pwm_23000

◆ DT_N_NODELABEL_pwm3

#define DT_N_NODELABEL_pwm3   DT_N_S_soc_S_peripheral_40000000_S_pwm_24000

◆ DT_N_NODELABEL_regulators

#define DT_N_NODELABEL_regulators   DT_N_S_soc_S_peripheral_40000000_S_regulator_4000

◆ DT_N_NODELABEL_rng_hci

#define DT_N_NODELABEL_rng_hci   DT_N_S_entropy_bt_hci

◆ DT_N_NODELABEL_rtc0

#define DT_N_NODELABEL_rtc0   DT_N_S_soc_S_peripheral_40000000_S_rtc_14000

◆ DT_N_NODELABEL_rtc1

#define DT_N_NODELABEL_rtc1   DT_N_S_soc_S_peripheral_40000000_S_rtc_15000

◆ DT_N_NODELABEL_scratch_partition

#define DT_N_NODELABEL_scratch_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000

◆ DT_N_NODELABEL_slot0_ns_partition

#define DT_N_NODELABEL_slot0_ns_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000

◆ DT_N_NODELABEL_slot0_partition

#define DT_N_NODELABEL_slot0_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000

◆ DT_N_NODELABEL_slot1_ns_partition

#define DT_N_NODELABEL_slot1_ns_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000

◆ DT_N_NODELABEL_slot1_partition

#define DT_N_NODELABEL_slot1_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000

◆ DT_N_NODELABEL_spi0

#define DT_N_NODELABEL_spi0   DT_N_S_soc_S_peripheral_40000000_S_spi_8000

◆ DT_N_NODELABEL_spi1

#define DT_N_NODELABEL_spi1   DT_N_S_soc_S_peripheral_40000000_S_spi_9000

◆ DT_N_NODELABEL_spi2

#define DT_N_NODELABEL_spi2   DT_N_S_soc_S_peripheral_40000000_S_spi_a000

◆ DT_N_NODELABEL_spi2_default

#define DT_N_NODELABEL_spi2_default   DT_N_S_pin_controller_S_spi2_default

◆ DT_N_NODELABEL_spi2_sleep

#define DT_N_NODELABEL_spi2_sleep   DT_N_S_pin_controller_S_spi2_sleep

◆ DT_N_NODELABEL_spi3

#define DT_N_NODELABEL_spi3   DT_N_S_soc_S_peripheral_40000000_S_spi_b000

◆ DT_N_NODELABEL_sram0

#define DT_N_NODELABEL_sram0   DT_N_S_soc_S_memory_20000000

◆ DT_N_NODELABEL_sram0_modem

#define DT_N_NODELABEL_sram0_modem   DT_N_S_reserved_memory_S_image_modem_20016000

◆ DT_N_NODELABEL_sram0_ns

#define DT_N_NODELABEL_sram0_ns   DT_N_S_reserved_memory_S_image_ns_20020000

◆ DT_N_NODELABEL_sram0_s

#define DT_N_NODELABEL_sram0_s   DT_N_S_reserved_memory_S_image_s_20000000

◆ DT_N_NODELABEL_storage_partition

#define DT_N_NODELABEL_storage_partition   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000

◆ DT_N_NODELABEL_systick

#define DT_N_NODELABEL_systick   DT_N_S_soc_S_timer_e000e010

◆ DT_N_NODELABEL_timer0

#define DT_N_NODELABEL_timer0   DT_N_S_soc_S_peripheral_40000000_S_timer_f000

◆ DT_N_NODELABEL_timer1

#define DT_N_NODELABEL_timer1   DT_N_S_soc_S_peripheral_40000000_S_timer_10000

◆ DT_N_NODELABEL_timer2

#define DT_N_NODELABEL_timer2   DT_N_S_soc_S_peripheral_40000000_S_timer_11000

◆ DT_N_NODELABEL_uart0

#define DT_N_NODELABEL_uart0   DT_N_S_soc_S_peripheral_40000000_S_uart_8000

◆ DT_N_NODELABEL_uart0_default

#define DT_N_NODELABEL_uart0_default   DT_N_S_pin_controller_S_uart0_default

◆ DT_N_NODELABEL_uart0_sleep

#define DT_N_NODELABEL_uart0_sleep   DT_N_S_pin_controller_S_uart0_sleep

◆ DT_N_NODELABEL_uart1

#define DT_N_NODELABEL_uart1   DT_N_S_soc_S_peripheral_40000000_S_uart_9000

◆ DT_N_NODELABEL_uart2

#define DT_N_NODELABEL_uart2   DT_N_S_soc_S_peripheral_40000000_S_uart_a000

◆ DT_N_NODELABEL_uart2_default

#define DT_N_NODELABEL_uart2_default   DT_N_S_pin_controller_S_uart2_default

◆ DT_N_NODELABEL_uart2_sleep

#define DT_N_NODELABEL_uart2_sleep   DT_N_S_pin_controller_S_uart2_sleep

◆ DT_N_NODELABEL_uart3

#define DT_N_NODELABEL_uart3   DT_N_S_soc_S_peripheral_40000000_S_uart_b000

◆ DT_N_NODELABEL_vmc

#define DT_N_NODELABEL_vmc   DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000

◆ DT_N_NODELABEL_wdt

#define DT_N_NODELABEL_wdt   DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000

◆ DT_N_NODELABEL_wdt0

#define DT_N_NODELABEL_wdt0   DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000

◆ DT_N_ORD

#define DT_N_ORD   0

◆ DT_N_P_compatible

#define DT_N_P_compatible   {"nordic,ltewatch_nrf9160"}

◆ DT_N_P_compatible_EXISTS

#define DT_N_P_compatible_EXISTS   1

◆ DT_N_P_compatible_FOREACH_PROP_ELEM

#define DT_N_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N, compatible, 0)

◆ DT_N_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N, compatible, 0, __VA_ARGS__)

◆ DT_N_P_compatible_IDX_0

#define DT_N_P_compatible_IDX_0   "nordic,ltewatch_nrf9160"

◆ DT_N_P_compatible_IDX_0_EXISTS

#define DT_N_P_compatible_IDX_0_EXISTS   1

◆ DT_N_P_compatible_IDX_0_TOKEN

#define DT_N_P_compatible_IDX_0_TOKEN   nordic_ltewatch_nrf9160

◆ DT_N_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_LTEWATCH_NRF9160

◆ DT_N_P_compatible_LEN

#define DT_N_P_compatible_LEN   1

◆ DT_N_PATH

#define DT_N_PATH   "/"

◆ DT_N_PINCTRL_NUM

#define DT_N_PINCTRL_NUM   0

◆ DT_N_RANGES_NUM

#define DT_N_RANGES_NUM   0

◆ DT_N_REG_NUM

#define DT_N_REG_NUM   0

◆ DT_N_REQUIRES_ORDS

#define DT_N_REQUIRES_ORDS   /* nothing */

◆ DT_N_S_aliases_CHILD_IDX

#define DT_N_S_aliases_CHILD_IDX   1

◆ DT_N_S_aliases_EXISTS

#define DT_N_S_aliases_EXISTS   1

◆ DT_N_S_aliases_FOREACH_CHILD

#define DT_N_S_aliases_FOREACH_CHILD (   fn)

◆ DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_aliases_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_aliases_FOREACH_CHILD_VARGS

#define DT_N_S_aliases_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_aliases_FOREACH_RANGE

#define DT_N_S_aliases_FOREACH_RANGE (   fn)

◆ DT_N_S_aliases_FULL_NAME

#define DT_N_S_aliases_FULL_NAME   "aliases"

◆ DT_N_S_aliases_IRQ_NUM

#define DT_N_S_aliases_IRQ_NUM   0

◆ DT_N_S_aliases_ORD

#define DT_N_S_aliases_ORD   1

◆ DT_N_S_aliases_PARENT

#define DT_N_S_aliases_PARENT   DT_N

◆ DT_N_S_aliases_PATH

#define DT_N_S_aliases_PATH   "/aliases"

◆ DT_N_S_aliases_PINCTRL_NUM

#define DT_N_S_aliases_PINCTRL_NUM   0

◆ DT_N_S_aliases_RANGES_NUM

#define DT_N_S_aliases_RANGES_NUM   0

◆ DT_N_S_aliases_REG_NUM

#define DT_N_S_aliases_REG_NUM   0

◆ DT_N_S_aliases_REQUIRES_ORDS

#define DT_N_S_aliases_REQUIRES_ORDS    0, /* / */

◆ DT_N_S_aliases_STATUS_okay

#define DT_N_S_aliases_STATUS_okay   1

◆ DT_N_S_aliases_SUPPORTS_ORDS

#define DT_N_S_aliases_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_buttons_CHILD_IDX

#define DT_N_S_buttons_CHILD_IDX   8

◆ DT_N_S_buttons_COMPAT_MATCHES_gpio_keys

#define DT_N_S_buttons_COMPAT_MATCHES_gpio_keys   1

◆ DT_N_S_buttons_EXISTS

#define DT_N_S_buttons_EXISTS   1

◆ DT_N_S_buttons_FOREACH_CHILD

#define DT_N_S_buttons_FOREACH_CHILD (   fn)    fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2)

◆ DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_buttons_S_button_0) fn(DT_N_S_buttons_S_button_1) fn(DT_N_S_buttons_S_button_2)

◆ DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_buttons_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__)

◆ DT_N_S_buttons_FOREACH_CHILD_VARGS

#define DT_N_S_buttons_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_buttons_S_button_0, __VA_ARGS__) fn(DT_N_S_buttons_S_button_1, __VA_ARGS__) fn(DT_N_S_buttons_S_button_2, __VA_ARGS__)

◆ DT_N_S_buttons_FOREACH_RANGE

#define DT_N_S_buttons_FOREACH_RANGE (   fn)

◆ DT_N_S_buttons_FULL_NAME

#define DT_N_S_buttons_FULL_NAME   "buttons"

◆ DT_N_S_buttons_IRQ_NUM

#define DT_N_S_buttons_IRQ_NUM   0

◆ DT_N_S_buttons_ORD

#define DT_N_S_buttons_ORD   11

◆ DT_N_S_buttons_P_compatible

#define DT_N_S_buttons_P_compatible   {"gpio-keys"}

◆ DT_N_S_buttons_P_compatible_EXISTS

#define DT_N_S_buttons_P_compatible_EXISTS   1

◆ DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_buttons, compatible, 0)

◆ DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_buttons_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_buttons, compatible, 0, __VA_ARGS__)

◆ DT_N_S_buttons_P_compatible_IDX_0

#define DT_N_S_buttons_P_compatible_IDX_0   "gpio-keys"

◆ DT_N_S_buttons_P_compatible_IDX_0_EXISTS

#define DT_N_S_buttons_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_buttons_P_compatible_IDX_0_TOKEN

#define DT_N_S_buttons_P_compatible_IDX_0_TOKEN   gpio_keys

◆ DT_N_S_buttons_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_buttons_P_compatible_IDX_0_UPPER_TOKEN   GPIO_KEYS

◆ DT_N_S_buttons_P_compatible_LEN

#define DT_N_S_buttons_P_compatible_LEN   1

◆ DT_N_S_buttons_PARENT

#define DT_N_S_buttons_PARENT   DT_N

◆ DT_N_S_buttons_PATH

#define DT_N_S_buttons_PATH   "/buttons"

◆ DT_N_S_buttons_PINCTRL_NUM

#define DT_N_S_buttons_PINCTRL_NUM   0

◆ DT_N_S_buttons_RANGES_NUM

#define DT_N_S_buttons_RANGES_NUM   0

◆ DT_N_S_buttons_REG_NUM

#define DT_N_S_buttons_REG_NUM   0

◆ DT_N_S_buttons_REQUIRES_ORDS

#define DT_N_S_buttons_REQUIRES_ORDS    0, /* / */

◆ DT_N_S_buttons_S_button_0_CHILD_IDX

#define DT_N_S_buttons_S_button_0_CHILD_IDX   0

◆ DT_N_S_buttons_S_button_0_EXISTS

#define DT_N_S_buttons_S_button_0_EXISTS   1

◆ DT_N_S_buttons_S_button_0_FOREACH_CHILD

#define DT_N_S_buttons_S_button_0_FOREACH_CHILD (   fn)

◆ DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_buttons_S_button_0_FOREACH_CHILD_VARGS

#define DT_N_S_buttons_S_button_0_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_buttons_S_button_0_FOREACH_RANGE

#define DT_N_S_buttons_S_button_0_FOREACH_RANGE (   fn)

◆ DT_N_S_buttons_S_button_0_FULL_NAME

#define DT_N_S_buttons_S_button_0_FULL_NAME   "button_0"

◆ DT_N_S_buttons_S_button_0_IRQ_NUM

#define DT_N_S_buttons_S_button_0_IRQ_NUM   0

◆ DT_N_S_buttons_S_button_0_ORD

#define DT_N_S_buttons_S_button_0_ORD   12

◆ DT_N_S_buttons_S_button_0_P_gpios_EXISTS

#define DT_N_S_buttons_S_button_0_P_gpios_EXISTS   1

◆ DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM

#define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_buttons_S_button_0, gpios, 0)

◆ DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_buttons_S_button_0_P_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_buttons_S_button_0, gpios, 0, __VA_ARGS__)

◆ DT_N_S_buttons_S_button_0_P_gpios_IDX_0_EXISTS

#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_EXISTS   1

◆ DT_N_S_buttons_S_button_0_P_gpios_IDX_0_PH

#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags

#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags   17

◆ DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin

#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin   19

◆ DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_buttons_S_button_0_P_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_buttons_S_button_0_P_gpios_LEN

#define DT_N_S_buttons_S_button_0_P_gpios_LEN   1

◆ DT_N_S_buttons_S_button_0_P_label

#define DT_N_S_buttons_S_button_0_P_label   "Push button 1"

◆ DT_N_S_buttons_S_button_0_P_label_EXISTS

#define DT_N_S_buttons_S_button_0_P_label_EXISTS   1

◆ DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM

#define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_buttons_S_button_0, label, 0) \
fn(DT_N_S_buttons_S_button_0, label, 1) \
fn(DT_N_S_buttons_S_button_0, label, 2) \
fn(DT_N_S_buttons_S_button_0, label, 3) \
fn(DT_N_S_buttons_S_button_0, label, 4) \
fn(DT_N_S_buttons_S_button_0, label, 5) \
fn(DT_N_S_buttons_S_button_0, label, 6) \
fn(DT_N_S_buttons_S_button_0, label, 7) \
fn(DT_N_S_buttons_S_button_0, label, 8) \
fn(DT_N_S_buttons_S_button_0, label, 9) \
fn(DT_N_S_buttons_S_button_0, label, 10) \
fn(DT_N_S_buttons_S_button_0, label, 11) \
fn(DT_N_S_buttons_S_button_0, label, 12)

◆ DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_buttons_S_button_0_P_label_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_buttons_S_button_0, label, 0, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_0, label, 1, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_0, label, 2, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_0, label, 3, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_0, label, 4, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_0, label, 5, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_0, label, 6, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_0, label, 7, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_0, label, 8, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_0, label, 9, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_0, label, 10, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_0, label, 11, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_0, label, 12, __VA_ARGS__)

◆ DT_N_S_buttons_S_button_0_P_label_STRING_TOKEN

#define DT_N_S_buttons_S_button_0_P_label_STRING_TOKEN   Push_button_1

◆ DT_N_S_buttons_S_button_0_P_label_STRING_UPPER_TOKEN

#define DT_N_S_buttons_S_button_0_P_label_STRING_UPPER_TOKEN   PUSH_BUTTON_1

◆ DT_N_S_buttons_S_button_0_PARENT

#define DT_N_S_buttons_S_button_0_PARENT   DT_N_S_buttons

◆ DT_N_S_buttons_S_button_0_PATH

#define DT_N_S_buttons_S_button_0_PATH   "/buttons/button_0"

◆ DT_N_S_buttons_S_button_0_PINCTRL_NUM

#define DT_N_S_buttons_S_button_0_PINCTRL_NUM   0

◆ DT_N_S_buttons_S_button_0_RANGES_NUM

#define DT_N_S_buttons_S_button_0_RANGES_NUM   0

◆ DT_N_S_buttons_S_button_0_REG_NUM

#define DT_N_S_buttons_S_button_0_REG_NUM   0

◆ DT_N_S_buttons_S_button_0_REQUIRES_ORDS

#define DT_N_S_buttons_S_button_0_REQUIRES_ORDS
Value:
9, /* /soc/peripheral@40000000/gpio@842500 */ \
11, /* /buttons */

◆ DT_N_S_buttons_S_button_0_STATUS_okay

#define DT_N_S_buttons_S_button_0_STATUS_okay   1

◆ DT_N_S_buttons_S_button_0_SUPPORTS_ORDS

#define DT_N_S_buttons_S_button_0_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_buttons_S_button_1_CHILD_IDX

#define DT_N_S_buttons_S_button_1_CHILD_IDX   1

◆ DT_N_S_buttons_S_button_1_EXISTS

#define DT_N_S_buttons_S_button_1_EXISTS   1

◆ DT_N_S_buttons_S_button_1_FOREACH_CHILD

#define DT_N_S_buttons_S_button_1_FOREACH_CHILD (   fn)

◆ DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_buttons_S_button_1_FOREACH_CHILD_VARGS

#define DT_N_S_buttons_S_button_1_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_buttons_S_button_1_FOREACH_RANGE

#define DT_N_S_buttons_S_button_1_FOREACH_RANGE (   fn)

◆ DT_N_S_buttons_S_button_1_FULL_NAME

#define DT_N_S_buttons_S_button_1_FULL_NAME   "button_1"

◆ DT_N_S_buttons_S_button_1_IRQ_NUM

#define DT_N_S_buttons_S_button_1_IRQ_NUM   0

◆ DT_N_S_buttons_S_button_1_ORD

#define DT_N_S_buttons_S_button_1_ORD   13

◆ DT_N_S_buttons_S_button_1_P_gpios_EXISTS

#define DT_N_S_buttons_S_button_1_P_gpios_EXISTS   1

◆ DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM

#define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_buttons_S_button_1, gpios, 0)

◆ DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_buttons_S_button_1_P_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_buttons_S_button_1, gpios, 0, __VA_ARGS__)

◆ DT_N_S_buttons_S_button_1_P_gpios_IDX_0_EXISTS

#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_EXISTS   1

◆ DT_N_S_buttons_S_button_1_P_gpios_IDX_0_PH

#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags

#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags   17

◆ DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin

#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin   18

◆ DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_buttons_S_button_1_P_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_buttons_S_button_1_P_gpios_LEN

#define DT_N_S_buttons_S_button_1_P_gpios_LEN   1

◆ DT_N_S_buttons_S_button_1_P_label

#define DT_N_S_buttons_S_button_1_P_label   "Push button 2"

◆ DT_N_S_buttons_S_button_1_P_label_EXISTS

#define DT_N_S_buttons_S_button_1_P_label_EXISTS   1

◆ DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM

#define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_buttons_S_button_1, label, 0) \
fn(DT_N_S_buttons_S_button_1, label, 1) \
fn(DT_N_S_buttons_S_button_1, label, 2) \
fn(DT_N_S_buttons_S_button_1, label, 3) \
fn(DT_N_S_buttons_S_button_1, label, 4) \
fn(DT_N_S_buttons_S_button_1, label, 5) \
fn(DT_N_S_buttons_S_button_1, label, 6) \
fn(DT_N_S_buttons_S_button_1, label, 7) \
fn(DT_N_S_buttons_S_button_1, label, 8) \
fn(DT_N_S_buttons_S_button_1, label, 9) \
fn(DT_N_S_buttons_S_button_1, label, 10) \
fn(DT_N_S_buttons_S_button_1, label, 11) \
fn(DT_N_S_buttons_S_button_1, label, 12)

◆ DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_buttons_S_button_1_P_label_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_buttons_S_button_1, label, 0, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_1, label, 1, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_1, label, 2, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_1, label, 3, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_1, label, 4, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_1, label, 5, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_1, label, 6, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_1, label, 7, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_1, label, 8, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_1, label, 9, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_1, label, 10, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_1, label, 11, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_1, label, 12, __VA_ARGS__)

◆ DT_N_S_buttons_S_button_1_P_label_STRING_TOKEN

#define DT_N_S_buttons_S_button_1_P_label_STRING_TOKEN   Push_button_2

◆ DT_N_S_buttons_S_button_1_P_label_STRING_UPPER_TOKEN

#define DT_N_S_buttons_S_button_1_P_label_STRING_UPPER_TOKEN   PUSH_BUTTON_2

◆ DT_N_S_buttons_S_button_1_PARENT

#define DT_N_S_buttons_S_button_1_PARENT   DT_N_S_buttons

◆ DT_N_S_buttons_S_button_1_PATH

#define DT_N_S_buttons_S_button_1_PATH   "/buttons/button_1"

◆ DT_N_S_buttons_S_button_1_PINCTRL_NUM

#define DT_N_S_buttons_S_button_1_PINCTRL_NUM   0

◆ DT_N_S_buttons_S_button_1_RANGES_NUM

#define DT_N_S_buttons_S_button_1_RANGES_NUM   0

◆ DT_N_S_buttons_S_button_1_REG_NUM

#define DT_N_S_buttons_S_button_1_REG_NUM   0

◆ DT_N_S_buttons_S_button_1_REQUIRES_ORDS

#define DT_N_S_buttons_S_button_1_REQUIRES_ORDS
Value:
9, /* /soc/peripheral@40000000/gpio@842500 */ \
11, /* /buttons */

◆ DT_N_S_buttons_S_button_1_STATUS_okay

#define DT_N_S_buttons_S_button_1_STATUS_okay   1

◆ DT_N_S_buttons_S_button_1_SUPPORTS_ORDS

#define DT_N_S_buttons_S_button_1_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_buttons_S_button_2_CHILD_IDX

#define DT_N_S_buttons_S_button_2_CHILD_IDX   2

◆ DT_N_S_buttons_S_button_2_EXISTS

#define DT_N_S_buttons_S_button_2_EXISTS   1

◆ DT_N_S_buttons_S_button_2_FOREACH_CHILD

#define DT_N_S_buttons_S_button_2_FOREACH_CHILD (   fn)

◆ DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_buttons_S_button_2_FOREACH_CHILD_VARGS

#define DT_N_S_buttons_S_button_2_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_buttons_S_button_2_FOREACH_RANGE

#define DT_N_S_buttons_S_button_2_FOREACH_RANGE (   fn)

◆ DT_N_S_buttons_S_button_2_FULL_NAME

#define DT_N_S_buttons_S_button_2_FULL_NAME   "button_2"

◆ DT_N_S_buttons_S_button_2_IRQ_NUM

#define DT_N_S_buttons_S_button_2_IRQ_NUM   0

◆ DT_N_S_buttons_S_button_2_ORD

#define DT_N_S_buttons_S_button_2_ORD   14

◆ DT_N_S_buttons_S_button_2_P_gpios_EXISTS

#define DT_N_S_buttons_S_button_2_P_gpios_EXISTS   1

◆ DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM

#define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_buttons_S_button_2, gpios, 0)

◆ DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_buttons_S_button_2_P_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_buttons_S_button_2, gpios, 0, __VA_ARGS__)

◆ DT_N_S_buttons_S_button_2_P_gpios_IDX_0_EXISTS

#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_EXISTS   1

◆ DT_N_S_buttons_S_button_2_P_gpios_IDX_0_PH

#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags

#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags   17

◆ DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin

#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin   17

◆ DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_buttons_S_button_2_P_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_buttons_S_button_2_P_gpios_LEN

#define DT_N_S_buttons_S_button_2_P_gpios_LEN   1

◆ DT_N_S_buttons_S_button_2_P_label

#define DT_N_S_buttons_S_button_2_P_label   "Switch 1"

◆ DT_N_S_buttons_S_button_2_P_label_EXISTS

#define DT_N_S_buttons_S_button_2_P_label_EXISTS   1

◆ DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM

#define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_buttons_S_button_2, label, 0) \
fn(DT_N_S_buttons_S_button_2, label, 1) \
fn(DT_N_S_buttons_S_button_2, label, 2) \
fn(DT_N_S_buttons_S_button_2, label, 3) \
fn(DT_N_S_buttons_S_button_2, label, 4) \
fn(DT_N_S_buttons_S_button_2, label, 5) \
fn(DT_N_S_buttons_S_button_2, label, 6) \
fn(DT_N_S_buttons_S_button_2, label, 7)

◆ DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_buttons_S_button_2_P_label_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_buttons_S_button_2, label, 0, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_2, label, 1, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_2, label, 2, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_2, label, 3, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_2, label, 4, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_2, label, 5, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_2, label, 6, __VA_ARGS__) \
fn(DT_N_S_buttons_S_button_2, label, 7, __VA_ARGS__)

◆ DT_N_S_buttons_S_button_2_P_label_STRING_TOKEN

#define DT_N_S_buttons_S_button_2_P_label_STRING_TOKEN   Switch_1

◆ DT_N_S_buttons_S_button_2_P_label_STRING_UPPER_TOKEN

#define DT_N_S_buttons_S_button_2_P_label_STRING_UPPER_TOKEN   SWITCH_1

◆ DT_N_S_buttons_S_button_2_PARENT

#define DT_N_S_buttons_S_button_2_PARENT   DT_N_S_buttons

◆ DT_N_S_buttons_S_button_2_PATH

#define DT_N_S_buttons_S_button_2_PATH   "/buttons/button_2"

◆ DT_N_S_buttons_S_button_2_PINCTRL_NUM

#define DT_N_S_buttons_S_button_2_PINCTRL_NUM   0

◆ DT_N_S_buttons_S_button_2_RANGES_NUM

#define DT_N_S_buttons_S_button_2_RANGES_NUM   0

◆ DT_N_S_buttons_S_button_2_REG_NUM

#define DT_N_S_buttons_S_button_2_REG_NUM   0

◆ DT_N_S_buttons_S_button_2_REQUIRES_ORDS

#define DT_N_S_buttons_S_button_2_REQUIRES_ORDS
Value:
9, /* /soc/peripheral@40000000/gpio@842500 */ \
11, /* /buttons */

◆ DT_N_S_buttons_S_button_2_STATUS_okay

#define DT_N_S_buttons_S_button_2_STATUS_okay   1

◆ DT_N_S_buttons_S_button_2_SUPPORTS_ORDS

#define DT_N_S_buttons_S_button_2_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_buttons_STATUS_okay

#define DT_N_S_buttons_STATUS_okay   1

◆ DT_N_S_buttons_SUPPORTS_ORDS

#define DT_N_S_buttons_SUPPORTS_ORDS
Value:
12, /* /buttons/button_0 */ \
13, /* /buttons/button_1 */ \
14, /* /buttons/button_2 */

◆ DT_N_S_chosen_CHILD_IDX

#define DT_N_S_chosen_CHILD_IDX   0

◆ DT_N_S_chosen_EXISTS

#define DT_N_S_chosen_EXISTS   1

◆ DT_N_S_chosen_FOREACH_CHILD

#define DT_N_S_chosen_FOREACH_CHILD (   fn)

◆ DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_chosen_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_chosen_FOREACH_CHILD_VARGS

#define DT_N_S_chosen_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_chosen_FOREACH_RANGE

#define DT_N_S_chosen_FOREACH_RANGE (   fn)

◆ DT_N_S_chosen_FULL_NAME

#define DT_N_S_chosen_FULL_NAME   "chosen"

◆ DT_N_S_chosen_IRQ_NUM

#define DT_N_S_chosen_IRQ_NUM   0

◆ DT_N_S_chosen_ORD

#define DT_N_S_chosen_ORD   2

◆ DT_N_S_chosen_PARENT

#define DT_N_S_chosen_PARENT   DT_N

◆ DT_N_S_chosen_PATH

#define DT_N_S_chosen_PATH   "/chosen"

◆ DT_N_S_chosen_PINCTRL_NUM

#define DT_N_S_chosen_PINCTRL_NUM   0

◆ DT_N_S_chosen_RANGES_NUM

#define DT_N_S_chosen_RANGES_NUM   0

◆ DT_N_S_chosen_REG_NUM

#define DT_N_S_chosen_REG_NUM   0

◆ DT_N_S_chosen_REQUIRES_ORDS

#define DT_N_S_chosen_REQUIRES_ORDS    0, /* / */

◆ DT_N_S_chosen_STATUS_okay

#define DT_N_S_chosen_STATUS_okay   1

◆ DT_N_S_chosen_SUPPORTS_ORDS

#define DT_N_S_chosen_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_cpus_CHILD_IDX

#define DT_N_S_cpus_CHILD_IDX   5

◆ DT_N_S_cpus_EXISTS

#define DT_N_S_cpus_EXISTS   1

◆ DT_N_S_cpus_FOREACH_CHILD

#define DT_N_S_cpus_FOREACH_CHILD (   fn)    fn(DT_N_S_cpus_S_cpu_0)

◆ DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_cpus_S_cpu_0)

◆ DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_cpus_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)

◆ DT_N_S_cpus_FOREACH_CHILD_VARGS

#define DT_N_S_cpus_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__)

◆ DT_N_S_cpus_FOREACH_RANGE

#define DT_N_S_cpus_FOREACH_RANGE (   fn)

◆ DT_N_S_cpus_FULL_NAME

#define DT_N_S_cpus_FULL_NAME   "cpus"

◆ DT_N_S_cpus_IRQ_NUM

#define DT_N_S_cpus_IRQ_NUM   0

◆ DT_N_S_cpus_ORD

#define DT_N_S_cpus_ORD   15

◆ DT_N_S_cpus_PARENT

#define DT_N_S_cpus_PARENT   DT_N

◆ DT_N_S_cpus_PATH

#define DT_N_S_cpus_PATH   "/cpus"

◆ DT_N_S_cpus_PINCTRL_NUM

#define DT_N_S_cpus_PINCTRL_NUM   0

◆ DT_N_S_cpus_RANGES_NUM

#define DT_N_S_cpus_RANGES_NUM   0

◆ DT_N_S_cpus_REG_NUM

#define DT_N_S_cpus_REG_NUM   0

◆ DT_N_S_cpus_REQUIRES_ORDS

#define DT_N_S_cpus_REQUIRES_ORDS    0, /* / */

◆ DT_N_S_cpus_S_cpu_0_CHILD_IDX

#define DT_N_S_cpus_S_cpu_0_CHILD_IDX   0

◆ DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_arm_cortex_m33f

#define DT_N_S_cpus_S_cpu_0_COMPAT_MATCHES_arm_cortex_m33f   1

◆ DT_N_S_cpus_S_cpu_0_EXISTS

#define DT_N_S_cpus_S_cpu_0_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_FOREACH_CHILD

#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD (   fn)    fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)

◆ DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90)

◆ DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)

◆ DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_VARGS

#define DT_N_S_cpus_S_cpu_0_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__)

◆ DT_N_S_cpus_S_cpu_0_FOREACH_RANGE

#define DT_N_S_cpus_S_cpu_0_FOREACH_RANGE (   fn)

◆ DT_N_S_cpus_S_cpu_0_FULL_NAME

#define DT_N_S_cpus_S_cpu_0_FULL_NAME   "cpu@0"

◆ DT_N_S_cpus_S_cpu_0_IRQ_NUM

#define DT_N_S_cpus_S_cpu_0_IRQ_NUM   0

◆ DT_N_S_cpus_S_cpu_0_ORD

#define DT_N_S_cpus_S_cpu_0_ORD   16

◆ DT_N_S_cpus_S_cpu_0_P_compatible

#define DT_N_S_cpus_S_cpu_0_P_compatible   {"arm,cortex-m33f"}

◆ DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS

#define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_cpus_S_cpu_0, compatible, 0)

◆ DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__)

◆ DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0

#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0   "arm,cortex-m33f"

◆ DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS

#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_TOKEN

#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_TOKEN   arm_cortex_m33f

◆ DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_UPPER_TOKEN   ARM_CORTEX_M33F

◆ DT_N_S_cpus_S_cpu_0_P_compatible_LEN

#define DT_N_S_cpus_S_cpu_0_P_compatible_LEN   1

◆ DT_N_S_cpus_S_cpu_0_P_reg

#define DT_N_S_cpus_S_cpu_0_P_reg   {0 /* 0x0 */}

◆ DT_N_S_cpus_S_cpu_0_P_reg_EXISTS

#define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_cpus_S_cpu_0, reg, 0)

◆ DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_cpus_S_cpu_0_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_cpus_S_cpu_0, reg, 0, __VA_ARGS__)

◆ DT_N_S_cpus_S_cpu_0_P_reg_IDX_0

#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0   0

◆ DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS

#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_P_wakeup_source

#define DT_N_S_cpus_S_cpu_0_P_wakeup_source   0

◆ DT_N_S_cpus_S_cpu_0_P_wakeup_source_EXISTS

#define DT_N_S_cpus_S_cpu_0_P_wakeup_source_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_PARENT

#define DT_N_S_cpus_S_cpu_0_PARENT   DT_N_S_cpus

◆ DT_N_S_cpus_S_cpu_0_PATH

#define DT_N_S_cpus_S_cpu_0_PATH   "/cpus/cpu@0"

◆ DT_N_S_cpus_S_cpu_0_PINCTRL_NUM

#define DT_N_S_cpus_S_cpu_0_PINCTRL_NUM   0

◆ DT_N_S_cpus_S_cpu_0_RANGES_NUM

#define DT_N_S_cpus_S_cpu_0_RANGES_NUM   0

◆ DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS

#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS   0 /* 0x0 */

◆ DT_N_S_cpus_S_cpu_0_REG_NUM

#define DT_N_S_cpus_S_cpu_0_REG_NUM   1

◆ DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS

#define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS    15, /* /cpus */

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_CHILD_IDX

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_CHILD_IDX   0

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MATCHES_arm_armv8m_mpu

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_COMPAT_MATCHES_arm_armv8m_mpu   1

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_EXISTS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD (   fn)

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_VARGS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_RANGE

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_RANGE (   fn)

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FULL_NAME

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FULL_NAME   "mpu@e000ed90"

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_IRQ_NUM

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_IRQ_NUM   0

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_ORD   17

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_arm_num_mpu_regions

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_arm_num_mpu_regions   16

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_arm_num_mpu_regions_EXISTS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_arm_num_mpu_regions_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible   {"arm,armv8m-mpu"}

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_EXISTS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0)

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0, __VA_ARGS__)

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0   "arm,armv8m-mpu"

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_EXISTS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_TOKEN

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_TOKEN   arm_armv8m_mpu

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_UPPER_TOKEN   ARM_ARMV8M_MPU

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_LEN

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_LEN   1

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg   {3758157200 /* 0xe000ed90 */, 64 /* 0x40 */}

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_EXISTS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 0) \
fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 1)

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 0, __VA_ARGS__) \
fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, reg, 1, __VA_ARGS__)

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0   3758157200

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0_EXISTS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1   64

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1_EXISTS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source   0

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source_EXISTS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PARENT

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PARENT   DT_N_S_cpus_S_cpu_0

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PATH

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PATH   "/cpus/cpu@0/mpu@e000ed90"

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PINCTRL_NUM

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PINCTRL_NUM   0

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_RANGES_NUM

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_RANGES_NUM   0

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_EXISTS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_EXISTS   1

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_ADDRESS   3758157200 /* 0xe000ed90 */

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_SIZE

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_SIZE   64 /* 0x40 */

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_NUM

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_NUM   1

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REQUIRES_ORDS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REQUIRES_ORDS    16, /* /cpus/cpu@0 */

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_STATUS_okay

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_STATUS_okay   1

◆ DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_SUPPORTS_ORDS

#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_cpus_S_cpu_0_STATUS_okay

#define DT_N_S_cpus_S_cpu_0_STATUS_okay   1

◆ DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS

#define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS    17, /* /cpus/cpu@0/mpu@e000ed90 */

◆ DT_N_S_cpus_STATUS_okay

#define DT_N_S_cpus_STATUS_okay   1

◆ DT_N_S_cpus_SUPPORTS_ORDS

#define DT_N_S_cpus_SUPPORTS_ORDS    16, /* /cpus/cpu@0 */

◆ DT_N_S_cryptocell_sw_CHILD_IDX

#define DT_N_S_cryptocell_sw_CHILD_IDX   6

◆ DT_N_S_cryptocell_sw_COMPAT_MATCHES_nordic_nrf_cc310_sw

#define DT_N_S_cryptocell_sw_COMPAT_MATCHES_nordic_nrf_cc310_sw   1

◆ DT_N_S_cryptocell_sw_EXISTS

#define DT_N_S_cryptocell_sw_EXISTS   1

◆ DT_N_S_cryptocell_sw_FOREACH_CHILD

#define DT_N_S_cryptocell_sw_FOREACH_CHILD (   fn)

◆ DT_N_S_cryptocell_sw_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_cryptocell_sw_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_cryptocell_sw_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_cryptocell_sw_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_cryptocell_sw_FOREACH_CHILD_VARGS

#define DT_N_S_cryptocell_sw_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_cryptocell_sw_FOREACH_RANGE

#define DT_N_S_cryptocell_sw_FOREACH_RANGE (   fn)

◆ DT_N_S_cryptocell_sw_FULL_NAME

#define DT_N_S_cryptocell_sw_FULL_NAME   "cryptocell-sw"

◆ DT_N_S_cryptocell_sw_IRQ_NUM

#define DT_N_S_cryptocell_sw_IRQ_NUM   0

◆ DT_N_S_cryptocell_sw_ORD

#define DT_N_S_cryptocell_sw_ORD   3

◆ DT_N_S_cryptocell_sw_P_compatible

#define DT_N_S_cryptocell_sw_P_compatible   {"nordic,nrf-cc310-sw"}

◆ DT_N_S_cryptocell_sw_P_compatible_EXISTS

#define DT_N_S_cryptocell_sw_P_compatible_EXISTS   1

◆ DT_N_S_cryptocell_sw_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_cryptocell_sw_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_cryptocell_sw, compatible, 0)

◆ DT_N_S_cryptocell_sw_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_cryptocell_sw_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_cryptocell_sw, compatible, 0, __VA_ARGS__)

◆ DT_N_S_cryptocell_sw_P_compatible_IDX_0

#define DT_N_S_cryptocell_sw_P_compatible_IDX_0   "nordic,nrf-cc310-sw"

◆ DT_N_S_cryptocell_sw_P_compatible_IDX_0_EXISTS

#define DT_N_S_cryptocell_sw_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_cryptocell_sw_P_compatible_IDX_0_TOKEN

#define DT_N_S_cryptocell_sw_P_compatible_IDX_0_TOKEN   nordic_nrf_cc310_sw

◆ DT_N_S_cryptocell_sw_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_cryptocell_sw_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_CC310_SW

◆ DT_N_S_cryptocell_sw_P_compatible_LEN

#define DT_N_S_cryptocell_sw_P_compatible_LEN   1

◆ DT_N_S_cryptocell_sw_P_label

#define DT_N_S_cryptocell_sw_P_label   "CRYPTOCELL_SW"

◆ DT_N_S_cryptocell_sw_P_label_EXISTS

#define DT_N_S_cryptocell_sw_P_label_EXISTS   1

◆ DT_N_S_cryptocell_sw_P_label_FOREACH_PROP_ELEM

#define DT_N_S_cryptocell_sw_P_label_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_cryptocell_sw, label, 0) \
fn(DT_N_S_cryptocell_sw, label, 1) \
fn(DT_N_S_cryptocell_sw, label, 2) \
fn(DT_N_S_cryptocell_sw, label, 3) \
fn(DT_N_S_cryptocell_sw, label, 4) \
fn(DT_N_S_cryptocell_sw, label, 5) \
fn(DT_N_S_cryptocell_sw, label, 6) \
fn(DT_N_S_cryptocell_sw, label, 7) \
fn(DT_N_S_cryptocell_sw, label, 8) \
fn(DT_N_S_cryptocell_sw, label, 9) \
fn(DT_N_S_cryptocell_sw, label, 10) \
fn(DT_N_S_cryptocell_sw, label, 11) \
fn(DT_N_S_cryptocell_sw, label, 12)

◆ DT_N_S_cryptocell_sw_P_label_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_cryptocell_sw_P_label_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_cryptocell_sw, label, 0, __VA_ARGS__) \
fn(DT_N_S_cryptocell_sw, label, 1, __VA_ARGS__) \
fn(DT_N_S_cryptocell_sw, label, 2, __VA_ARGS__) \
fn(DT_N_S_cryptocell_sw, label, 3, __VA_ARGS__) \
fn(DT_N_S_cryptocell_sw, label, 4, __VA_ARGS__) \
fn(DT_N_S_cryptocell_sw, label, 5, __VA_ARGS__) \
fn(DT_N_S_cryptocell_sw, label, 6, __VA_ARGS__) \
fn(DT_N_S_cryptocell_sw, label, 7, __VA_ARGS__) \
fn(DT_N_S_cryptocell_sw, label, 8, __VA_ARGS__) \
fn(DT_N_S_cryptocell_sw, label, 9, __VA_ARGS__) \
fn(DT_N_S_cryptocell_sw, label, 10, __VA_ARGS__) \
fn(DT_N_S_cryptocell_sw, label, 11, __VA_ARGS__) \
fn(DT_N_S_cryptocell_sw, label, 12, __VA_ARGS__)

◆ DT_N_S_cryptocell_sw_P_label_STRING_TOKEN

#define DT_N_S_cryptocell_sw_P_label_STRING_TOKEN   CRYPTOCELL_SW

◆ DT_N_S_cryptocell_sw_P_label_STRING_UPPER_TOKEN

#define DT_N_S_cryptocell_sw_P_label_STRING_UPPER_TOKEN   CRYPTOCELL_SW

◆ DT_N_S_cryptocell_sw_P_status

#define DT_N_S_cryptocell_sw_P_status   "okay"

◆ DT_N_S_cryptocell_sw_P_status_ENUM_IDX

#define DT_N_S_cryptocell_sw_P_status_ENUM_IDX   1

◆ DT_N_S_cryptocell_sw_P_status_ENUM_TOKEN

#define DT_N_S_cryptocell_sw_P_status_ENUM_TOKEN   okay

◆ DT_N_S_cryptocell_sw_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_cryptocell_sw_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_cryptocell_sw_P_status_EXISTS

#define DT_N_S_cryptocell_sw_P_status_EXISTS   1

◆ DT_N_S_cryptocell_sw_P_status_FOREACH_PROP_ELEM

#define DT_N_S_cryptocell_sw_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_cryptocell_sw, status, 0) \
fn(DT_N_S_cryptocell_sw, status, 1) \
fn(DT_N_S_cryptocell_sw, status, 2) \
fn(DT_N_S_cryptocell_sw, status, 3)

◆ DT_N_S_cryptocell_sw_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_cryptocell_sw_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_cryptocell_sw, status, 0, __VA_ARGS__) \
fn(DT_N_S_cryptocell_sw, status, 1, __VA_ARGS__) \
fn(DT_N_S_cryptocell_sw, status, 2, __VA_ARGS__) \
fn(DT_N_S_cryptocell_sw, status, 3, __VA_ARGS__)

◆ DT_N_S_cryptocell_sw_P_status_STRING_TOKEN

#define DT_N_S_cryptocell_sw_P_status_STRING_TOKEN   okay

◆ DT_N_S_cryptocell_sw_P_status_STRING_UPPER_TOKEN

#define DT_N_S_cryptocell_sw_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_cryptocell_sw_P_wakeup_source

#define DT_N_S_cryptocell_sw_P_wakeup_source   0

◆ DT_N_S_cryptocell_sw_P_wakeup_source_EXISTS

#define DT_N_S_cryptocell_sw_P_wakeup_source_EXISTS   1

◆ DT_N_S_cryptocell_sw_PARENT

#define DT_N_S_cryptocell_sw_PARENT   DT_N

◆ DT_N_S_cryptocell_sw_PATH

#define DT_N_S_cryptocell_sw_PATH   "/cryptocell-sw"

◆ DT_N_S_cryptocell_sw_PINCTRL_NUM

#define DT_N_S_cryptocell_sw_PINCTRL_NUM   0

◆ DT_N_S_cryptocell_sw_RANGES_NUM

#define DT_N_S_cryptocell_sw_RANGES_NUM   0

◆ DT_N_S_cryptocell_sw_REG_NUM

#define DT_N_S_cryptocell_sw_REG_NUM   0

◆ DT_N_S_cryptocell_sw_REQUIRES_ORDS

#define DT_N_S_cryptocell_sw_REQUIRES_ORDS    0, /* / */

◆ DT_N_S_cryptocell_sw_STATUS_okay

#define DT_N_S_cryptocell_sw_STATUS_okay   1

◆ DT_N_S_cryptocell_sw_SUPPORTS_ORDS

#define DT_N_S_cryptocell_sw_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_entropy_bt_hci_CHILD_IDX

#define DT_N_S_entropy_bt_hci_CHILD_IDX   4

◆ DT_N_S_entropy_bt_hci_COMPAT_MATCHES_zephyr_bt_hci_entropy

#define DT_N_S_entropy_bt_hci_COMPAT_MATCHES_zephyr_bt_hci_entropy   1

◆ DT_N_S_entropy_bt_hci_EXISTS

#define DT_N_S_entropy_bt_hci_EXISTS   1

◆ DT_N_S_entropy_bt_hci_FOREACH_CHILD

#define DT_N_S_entropy_bt_hci_FOREACH_CHILD (   fn)

◆ DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_entropy_bt_hci_FOREACH_CHILD_VARGS

#define DT_N_S_entropy_bt_hci_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_entropy_bt_hci_FOREACH_RANGE

#define DT_N_S_entropy_bt_hci_FOREACH_RANGE (   fn)

◆ DT_N_S_entropy_bt_hci_FULL_NAME

#define DT_N_S_entropy_bt_hci_FULL_NAME   "entropy_bt_hci"

◆ DT_N_S_entropy_bt_hci_IRQ_NUM

#define DT_N_S_entropy_bt_hci_IRQ_NUM   0

◆ DT_N_S_entropy_bt_hci_ORD

#define DT_N_S_entropy_bt_hci_ORD   4

◆ DT_N_S_entropy_bt_hci_P_compatible

#define DT_N_S_entropy_bt_hci_P_compatible   {"zephyr,bt-hci-entropy"}

◆ DT_N_S_entropy_bt_hci_P_compatible_EXISTS

#define DT_N_S_entropy_bt_hci_P_compatible_EXISTS   1

◆ DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_entropy_bt_hci, compatible, 0)

◆ DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_entropy_bt_hci_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_entropy_bt_hci, compatible, 0, __VA_ARGS__)

◆ DT_N_S_entropy_bt_hci_P_compatible_IDX_0

#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0   "zephyr,bt-hci-entropy"

◆ DT_N_S_entropy_bt_hci_P_compatible_IDX_0_EXISTS

#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_entropy_bt_hci_P_compatible_IDX_0_TOKEN

#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_TOKEN   zephyr_bt_hci_entropy

◆ DT_N_S_entropy_bt_hci_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_entropy_bt_hci_P_compatible_IDX_0_UPPER_TOKEN   ZEPHYR_BT_HCI_ENTROPY

◆ DT_N_S_entropy_bt_hci_P_compatible_LEN

#define DT_N_S_entropy_bt_hci_P_compatible_LEN   1

◆ DT_N_S_entropy_bt_hci_P_status

#define DT_N_S_entropy_bt_hci_P_status   "okay"

◆ DT_N_S_entropy_bt_hci_P_status_ENUM_IDX

#define DT_N_S_entropy_bt_hci_P_status_ENUM_IDX   1

◆ DT_N_S_entropy_bt_hci_P_status_ENUM_TOKEN

#define DT_N_S_entropy_bt_hci_P_status_ENUM_TOKEN   okay

◆ DT_N_S_entropy_bt_hci_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_entropy_bt_hci_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_entropy_bt_hci_P_status_EXISTS

#define DT_N_S_entropy_bt_hci_P_status_EXISTS   1

◆ DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM

#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_entropy_bt_hci, status, 0) \
fn(DT_N_S_entropy_bt_hci, status, 1) \
fn(DT_N_S_entropy_bt_hci, status, 2) \
fn(DT_N_S_entropy_bt_hci, status, 3)

◆ DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_entropy_bt_hci_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_entropy_bt_hci, status, 0, __VA_ARGS__) \
fn(DT_N_S_entropy_bt_hci, status, 1, __VA_ARGS__) \
fn(DT_N_S_entropy_bt_hci, status, 2, __VA_ARGS__) \
fn(DT_N_S_entropy_bt_hci, status, 3, __VA_ARGS__)

◆ DT_N_S_entropy_bt_hci_P_status_STRING_TOKEN

#define DT_N_S_entropy_bt_hci_P_status_STRING_TOKEN   okay

◆ DT_N_S_entropy_bt_hci_P_status_STRING_UPPER_TOKEN

#define DT_N_S_entropy_bt_hci_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_entropy_bt_hci_P_wakeup_source

#define DT_N_S_entropy_bt_hci_P_wakeup_source   0

◆ DT_N_S_entropy_bt_hci_P_wakeup_source_EXISTS

#define DT_N_S_entropy_bt_hci_P_wakeup_source_EXISTS   1

◆ DT_N_S_entropy_bt_hci_PARENT

#define DT_N_S_entropy_bt_hci_PARENT   DT_N

◆ DT_N_S_entropy_bt_hci_PATH

#define DT_N_S_entropy_bt_hci_PATH   "/entropy_bt_hci"

◆ DT_N_S_entropy_bt_hci_PINCTRL_NUM

#define DT_N_S_entropy_bt_hci_PINCTRL_NUM   0

◆ DT_N_S_entropy_bt_hci_RANGES_NUM

#define DT_N_S_entropy_bt_hci_RANGES_NUM   0

◆ DT_N_S_entropy_bt_hci_REG_NUM

#define DT_N_S_entropy_bt_hci_REG_NUM   0

◆ DT_N_S_entropy_bt_hci_REQUIRES_ORDS

#define DT_N_S_entropy_bt_hci_REQUIRES_ORDS    0, /* / */

◆ DT_N_S_entropy_bt_hci_STATUS_okay

#define DT_N_S_entropy_bt_hci_STATUS_okay   1

◆ DT_N_S_entropy_bt_hci_SUPPORTS_ORDS

#define DT_N_S_entropy_bt_hci_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_leds_CHILD_IDX

#define DT_N_S_leds_CHILD_IDX   7

◆ DT_N_S_leds_COMPAT_MATCHES_gpio_leds

#define DT_N_S_leds_COMPAT_MATCHES_gpio_leds   1

◆ DT_N_S_leds_EXISTS

#define DT_N_S_leds_EXISTS   1

◆ DT_N_S_leds_FOREACH_CHILD

#define DT_N_S_leds_FOREACH_CHILD (   fn)    fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2)

◆ DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2)

◆ DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_leds_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__)

◆ DT_N_S_leds_FOREACH_CHILD_VARGS

#define DT_N_S_leds_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__)

◆ DT_N_S_leds_FOREACH_RANGE

#define DT_N_S_leds_FOREACH_RANGE (   fn)

◆ DT_N_S_leds_FULL_NAME

#define DT_N_S_leds_FULL_NAME   "leds"

◆ DT_N_S_leds_IRQ_NUM

#define DT_N_S_leds_IRQ_NUM   0

◆ DT_N_S_leds_ORD

#define DT_N_S_leds_ORD   18

◆ DT_N_S_leds_P_compatible

#define DT_N_S_leds_P_compatible   {"gpio-leds"}

◆ DT_N_S_leds_P_compatible_EXISTS

#define DT_N_S_leds_P_compatible_EXISTS   1

◆ DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_leds, compatible, 0)

◆ DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_leds, compatible, 0, __VA_ARGS__)

◆ DT_N_S_leds_P_compatible_IDX_0

#define DT_N_S_leds_P_compatible_IDX_0   "gpio-leds"

◆ DT_N_S_leds_P_compatible_IDX_0_EXISTS

#define DT_N_S_leds_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_leds_P_compatible_IDX_0_TOKEN

#define DT_N_S_leds_P_compatible_IDX_0_TOKEN   gpio_leds

◆ DT_N_S_leds_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_leds_P_compatible_IDX_0_UPPER_TOKEN   GPIO_LEDS

◆ DT_N_S_leds_P_compatible_LEN

#define DT_N_S_leds_P_compatible_LEN   1

◆ DT_N_S_leds_PARENT

#define DT_N_S_leds_PARENT   DT_N

◆ DT_N_S_leds_PATH

#define DT_N_S_leds_PATH   "/leds"

◆ DT_N_S_leds_PINCTRL_NUM

#define DT_N_S_leds_PINCTRL_NUM   0

◆ DT_N_S_leds_RANGES_NUM

#define DT_N_S_leds_RANGES_NUM   0

◆ DT_N_S_leds_REG_NUM

#define DT_N_S_leds_REG_NUM   0

◆ DT_N_S_leds_REQUIRES_ORDS

#define DT_N_S_leds_REQUIRES_ORDS    0, /* / */

◆ DT_N_S_leds_S_led_0_CHILD_IDX

#define DT_N_S_leds_S_led_0_CHILD_IDX   0

◆ DT_N_S_leds_S_led_0_EXISTS

#define DT_N_S_leds_S_led_0_EXISTS   1

◆ DT_N_S_leds_S_led_0_FOREACH_CHILD

#define DT_N_S_leds_S_led_0_FOREACH_CHILD (   fn)

◆ DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_leds_S_led_0_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_leds_S_led_0_FOREACH_CHILD_VARGS

#define DT_N_S_leds_S_led_0_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_leds_S_led_0_FOREACH_RANGE

#define DT_N_S_leds_S_led_0_FOREACH_RANGE (   fn)

◆ DT_N_S_leds_S_led_0_FULL_NAME

#define DT_N_S_leds_S_led_0_FULL_NAME   "led_0"

◆ DT_N_S_leds_S_led_0_IRQ_NUM

#define DT_N_S_leds_S_led_0_IRQ_NUM   0

◆ DT_N_S_leds_S_led_0_ORD

#define DT_N_S_leds_S_led_0_ORD   19

◆ DT_N_S_leds_S_led_0_P_gpios_EXISTS

#define DT_N_S_leds_S_led_0_P_gpios_EXISTS   1

◆ DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM

#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_leds_S_led_0, gpios, 0)

◆ DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_leds_S_led_0_P_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_leds_S_led_0, gpios, 0, __VA_ARGS__)

◆ DT_N_S_leds_S_led_0_P_gpios_IDX_0_EXISTS

#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_EXISTS   1

◆ DT_N_S_leds_S_led_0_P_gpios_IDX_0_PH

#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags

#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags   0

◆ DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin

#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin   15

◆ DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_leds_S_led_0_P_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_leds_S_led_0_P_gpios_LEN

#define DT_N_S_leds_S_led_0_P_gpios_LEN   1

◆ DT_N_S_leds_S_led_0_P_label

#define DT_N_S_leds_S_led_0_P_label   "Green LED 1"

◆ DT_N_S_leds_S_led_0_P_label_EXISTS

#define DT_N_S_leds_S_led_0_P_label_EXISTS   1

◆ DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM

#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_leds_S_led_0, label, 0) \
fn(DT_N_S_leds_S_led_0, label, 1) \
fn(DT_N_S_leds_S_led_0, label, 2) \
fn(DT_N_S_leds_S_led_0, label, 3) \
fn(DT_N_S_leds_S_led_0, label, 4) \
fn(DT_N_S_leds_S_led_0, label, 5) \
fn(DT_N_S_leds_S_led_0, label, 6) \
fn(DT_N_S_leds_S_led_0, label, 7) \
fn(DT_N_S_leds_S_led_0, label, 8) \
fn(DT_N_S_leds_S_led_0, label, 9) \
fn(DT_N_S_leds_S_led_0, label, 10)

◆ DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_leds_S_led_0_P_label_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_leds_S_led_0, label, 0, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_0, label, 1, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_0, label, 2, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_0, label, 3, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_0, label, 4, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_0, label, 5, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_0, label, 6, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_0, label, 7, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_0, label, 8, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_0, label, 9, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_0, label, 10, __VA_ARGS__)

◆ DT_N_S_leds_S_led_0_P_label_STRING_TOKEN

#define DT_N_S_leds_S_led_0_P_label_STRING_TOKEN   Green_LED_1

◆ DT_N_S_leds_S_led_0_P_label_STRING_UPPER_TOKEN

#define DT_N_S_leds_S_led_0_P_label_STRING_UPPER_TOKEN   GREEN_LED_1

◆ DT_N_S_leds_S_led_0_PARENT

#define DT_N_S_leds_S_led_0_PARENT   DT_N_S_leds

◆ DT_N_S_leds_S_led_0_PATH

#define DT_N_S_leds_S_led_0_PATH   "/leds/led_0"

◆ DT_N_S_leds_S_led_0_PINCTRL_NUM

#define DT_N_S_leds_S_led_0_PINCTRL_NUM   0

◆ DT_N_S_leds_S_led_0_RANGES_NUM

#define DT_N_S_leds_S_led_0_RANGES_NUM   0

◆ DT_N_S_leds_S_led_0_REG_NUM

#define DT_N_S_leds_S_led_0_REG_NUM   0

◆ DT_N_S_leds_S_led_0_REQUIRES_ORDS

#define DT_N_S_leds_S_led_0_REQUIRES_ORDS
Value:
9, /* /soc/peripheral@40000000/gpio@842500 */ \
18, /* /leds */

◆ DT_N_S_leds_S_led_0_STATUS_okay

#define DT_N_S_leds_S_led_0_STATUS_okay   1

◆ DT_N_S_leds_S_led_0_SUPPORTS_ORDS

#define DT_N_S_leds_S_led_0_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_leds_S_led_1_CHILD_IDX

#define DT_N_S_leds_S_led_1_CHILD_IDX   1

◆ DT_N_S_leds_S_led_1_EXISTS

#define DT_N_S_leds_S_led_1_EXISTS   1

◆ DT_N_S_leds_S_led_1_FOREACH_CHILD

#define DT_N_S_leds_S_led_1_FOREACH_CHILD (   fn)

◆ DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_leds_S_led_1_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_leds_S_led_1_FOREACH_CHILD_VARGS

#define DT_N_S_leds_S_led_1_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_leds_S_led_1_FOREACH_RANGE

#define DT_N_S_leds_S_led_1_FOREACH_RANGE (   fn)

◆ DT_N_S_leds_S_led_1_FULL_NAME

#define DT_N_S_leds_S_led_1_FULL_NAME   "led_1"

◆ DT_N_S_leds_S_led_1_IRQ_NUM

#define DT_N_S_leds_S_led_1_IRQ_NUM   0

◆ DT_N_S_leds_S_led_1_ORD

#define DT_N_S_leds_S_led_1_ORD   20

◆ DT_N_S_leds_S_led_1_P_gpios_EXISTS

#define DT_N_S_leds_S_led_1_P_gpios_EXISTS   1

◆ DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM

#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_leds_S_led_1, gpios, 0)

◆ DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_leds_S_led_1_P_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_leds_S_led_1, gpios, 0, __VA_ARGS__)

◆ DT_N_S_leds_S_led_1_P_gpios_IDX_0_EXISTS

#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_EXISTS   1

◆ DT_N_S_leds_S_led_1_P_gpios_IDX_0_PH

#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags

#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags   0

◆ DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin

#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin   14

◆ DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_leds_S_led_1_P_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_leds_S_led_1_P_gpios_LEN

#define DT_N_S_leds_S_led_1_P_gpios_LEN   1

◆ DT_N_S_leds_S_led_1_P_label

#define DT_N_S_leds_S_led_1_P_label   "Green LED 2"

◆ DT_N_S_leds_S_led_1_P_label_EXISTS

#define DT_N_S_leds_S_led_1_P_label_EXISTS   1

◆ DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM

#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_leds_S_led_1, label, 0) \
fn(DT_N_S_leds_S_led_1, label, 1) \
fn(DT_N_S_leds_S_led_1, label, 2) \
fn(DT_N_S_leds_S_led_1, label, 3) \
fn(DT_N_S_leds_S_led_1, label, 4) \
fn(DT_N_S_leds_S_led_1, label, 5) \
fn(DT_N_S_leds_S_led_1, label, 6) \
fn(DT_N_S_leds_S_led_1, label, 7) \
fn(DT_N_S_leds_S_led_1, label, 8) \
fn(DT_N_S_leds_S_led_1, label, 9) \
fn(DT_N_S_leds_S_led_1, label, 10)

◆ DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_leds_S_led_1_P_label_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_leds_S_led_1, label, 0, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_1, label, 1, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_1, label, 2, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_1, label, 3, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_1, label, 4, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_1, label, 5, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_1, label, 6, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_1, label, 7, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_1, label, 8, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_1, label, 9, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_1, label, 10, __VA_ARGS__)

◆ DT_N_S_leds_S_led_1_P_label_STRING_TOKEN

#define DT_N_S_leds_S_led_1_P_label_STRING_TOKEN   Green_LED_2

◆ DT_N_S_leds_S_led_1_P_label_STRING_UPPER_TOKEN

#define DT_N_S_leds_S_led_1_P_label_STRING_UPPER_TOKEN   GREEN_LED_2

◆ DT_N_S_leds_S_led_1_PARENT

#define DT_N_S_leds_S_led_1_PARENT   DT_N_S_leds

◆ DT_N_S_leds_S_led_1_PATH

#define DT_N_S_leds_S_led_1_PATH   "/leds/led_1"

◆ DT_N_S_leds_S_led_1_PINCTRL_NUM

#define DT_N_S_leds_S_led_1_PINCTRL_NUM   0

◆ DT_N_S_leds_S_led_1_RANGES_NUM

#define DT_N_S_leds_S_led_1_RANGES_NUM   0

◆ DT_N_S_leds_S_led_1_REG_NUM

#define DT_N_S_leds_S_led_1_REG_NUM   0

◆ DT_N_S_leds_S_led_1_REQUIRES_ORDS

#define DT_N_S_leds_S_led_1_REQUIRES_ORDS
Value:
9, /* /soc/peripheral@40000000/gpio@842500 */ \
18, /* /leds */

◆ DT_N_S_leds_S_led_1_STATUS_okay

#define DT_N_S_leds_S_led_1_STATUS_okay   1

◆ DT_N_S_leds_S_led_1_SUPPORTS_ORDS

#define DT_N_S_leds_S_led_1_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_leds_S_led_2_CHILD_IDX

#define DT_N_S_leds_S_led_2_CHILD_IDX   2

◆ DT_N_S_leds_S_led_2_EXISTS

#define DT_N_S_leds_S_led_2_EXISTS   1

◆ DT_N_S_leds_S_led_2_FOREACH_CHILD

#define DT_N_S_leds_S_led_2_FOREACH_CHILD (   fn)

◆ DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_leds_S_led_2_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_leds_S_led_2_FOREACH_CHILD_VARGS

#define DT_N_S_leds_S_led_2_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_leds_S_led_2_FOREACH_RANGE

#define DT_N_S_leds_S_led_2_FOREACH_RANGE (   fn)

◆ DT_N_S_leds_S_led_2_FULL_NAME

#define DT_N_S_leds_S_led_2_FULL_NAME   "led_2"

◆ DT_N_S_leds_S_led_2_IRQ_NUM

#define DT_N_S_leds_S_led_2_IRQ_NUM   0

◆ DT_N_S_leds_S_led_2_ORD

#define DT_N_S_leds_S_led_2_ORD   21

◆ DT_N_S_leds_S_led_2_P_gpios_EXISTS

#define DT_N_S_leds_S_led_2_P_gpios_EXISTS   1

◆ DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM

#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_leds_S_led_2, gpios, 0)

◆ DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_leds_S_led_2_P_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_leds_S_led_2, gpios, 0, __VA_ARGS__)

◆ DT_N_S_leds_S_led_2_P_gpios_IDX_0_EXISTS

#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_EXISTS   1

◆ DT_N_S_leds_S_led_2_P_gpios_IDX_0_PH

#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags

#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags   0

◆ DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin

#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin   13

◆ DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_leds_S_led_2_P_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_leds_S_led_2_P_gpios_LEN

#define DT_N_S_leds_S_led_2_P_gpios_LEN   1

◆ DT_N_S_leds_S_led_2_P_label

#define DT_N_S_leds_S_led_2_P_label   "Green LED 3"

◆ DT_N_S_leds_S_led_2_P_label_EXISTS

#define DT_N_S_leds_S_led_2_P_label_EXISTS   1

◆ DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM

#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_leds_S_led_2, label, 0) \
fn(DT_N_S_leds_S_led_2, label, 1) \
fn(DT_N_S_leds_S_led_2, label, 2) \
fn(DT_N_S_leds_S_led_2, label, 3) \
fn(DT_N_S_leds_S_led_2, label, 4) \
fn(DT_N_S_leds_S_led_2, label, 5) \
fn(DT_N_S_leds_S_led_2, label, 6) \
fn(DT_N_S_leds_S_led_2, label, 7) \
fn(DT_N_S_leds_S_led_2, label, 8) \
fn(DT_N_S_leds_S_led_2, label, 9) \
fn(DT_N_S_leds_S_led_2, label, 10)

◆ DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_leds_S_led_2_P_label_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_leds_S_led_2, label, 0, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_2, label, 1, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_2, label, 2, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_2, label, 3, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_2, label, 4, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_2, label, 5, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_2, label, 6, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_2, label, 7, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_2, label, 8, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_2, label, 9, __VA_ARGS__) \
fn(DT_N_S_leds_S_led_2, label, 10, __VA_ARGS__)

◆ DT_N_S_leds_S_led_2_P_label_STRING_TOKEN

#define DT_N_S_leds_S_led_2_P_label_STRING_TOKEN   Green_LED_3

◆ DT_N_S_leds_S_led_2_P_label_STRING_UPPER_TOKEN

#define DT_N_S_leds_S_led_2_P_label_STRING_UPPER_TOKEN   GREEN_LED_3

◆ DT_N_S_leds_S_led_2_PARENT

#define DT_N_S_leds_S_led_2_PARENT   DT_N_S_leds

◆ DT_N_S_leds_S_led_2_PATH

#define DT_N_S_leds_S_led_2_PATH   "/leds/led_2"

◆ DT_N_S_leds_S_led_2_PINCTRL_NUM

#define DT_N_S_leds_S_led_2_PINCTRL_NUM   0

◆ DT_N_S_leds_S_led_2_RANGES_NUM

#define DT_N_S_leds_S_led_2_RANGES_NUM   0

◆ DT_N_S_leds_S_led_2_REG_NUM

#define DT_N_S_leds_S_led_2_REG_NUM   0

◆ DT_N_S_leds_S_led_2_REQUIRES_ORDS

#define DT_N_S_leds_S_led_2_REQUIRES_ORDS
Value:
9, /* /soc/peripheral@40000000/gpio@842500 */ \
18, /* /leds */

◆ DT_N_S_leds_S_led_2_STATUS_okay

#define DT_N_S_leds_S_led_2_STATUS_okay   1

◆ DT_N_S_leds_S_led_2_SUPPORTS_ORDS

#define DT_N_S_leds_S_led_2_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_leds_STATUS_okay

#define DT_N_S_leds_STATUS_okay   1

◆ DT_N_S_leds_SUPPORTS_ORDS

#define DT_N_S_leds_SUPPORTS_ORDS
Value:
19, /* /leds/led_0 */ \
20, /* /leds/led_1 */ \
21, /* /leds/led_2 */

◆ DT_N_S_pin_controller_CHILD_IDX

#define DT_N_S_pin_controller_CHILD_IDX   3

◆ DT_N_S_pin_controller_COMPAT_MATCHES_nordic_nrf_pinctrl

#define DT_N_S_pin_controller_COMPAT_MATCHES_nordic_nrf_pinctrl   1

◆ DT_N_S_pin_controller_EXISTS

#define DT_N_S_pin_controller_EXISTS   1

◆ DT_N_S_pin_controller_FOREACH_CHILD

#define DT_N_S_pin_controller_FOREACH_CHILD (   fn)    fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart2_default) fn(DT_N_S_pin_controller_S_uart2_sleep) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_spi2_default) fn(DT_N_S_pin_controller_S_spi2_sleep)

◆ DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_pin_controller_S_uart0_default) fn(DT_N_S_pin_controller_S_uart0_sleep) fn(DT_N_S_pin_controller_S_uart2_default) fn(DT_N_S_pin_controller_S_uart2_sleep) fn(DT_N_S_pin_controller_S_i2c1_default) fn(DT_N_S_pin_controller_S_i2c1_sleep) fn(DT_N_S_pin_controller_S_spi2_default) fn(DT_N_S_pin_controller_S_spi2_sleep)

◆ DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_sleep, __VA_ARGS__)

◆ DT_N_S_pin_controller_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_uart0_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart2_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_i2c1_sleep, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_default, __VA_ARGS__) fn(DT_N_S_pin_controller_S_spi2_sleep, __VA_ARGS__)

◆ DT_N_S_pin_controller_FOREACH_RANGE

#define DT_N_S_pin_controller_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_FULL_NAME

#define DT_N_S_pin_controller_FULL_NAME   "pin-controller"

◆ DT_N_S_pin_controller_IRQ_NUM

#define DT_N_S_pin_controller_IRQ_NUM   0

◆ DT_N_S_pin_controller_ORD

#define DT_N_S_pin_controller_ORD   22

◆ DT_N_S_pin_controller_P_compatible

#define DT_N_S_pin_controller_P_compatible   {"nordic,nrf-pinctrl"}

◆ DT_N_S_pin_controller_P_compatible_EXISTS

#define DT_N_S_pin_controller_P_compatible_EXISTS   1

◆ DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_pin_controller, compatible, 0)

◆ DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_pin_controller_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller, compatible, 0, __VA_ARGS__)

◆ DT_N_S_pin_controller_P_compatible_IDX_0

#define DT_N_S_pin_controller_P_compatible_IDX_0   "nordic,nrf-pinctrl"

◆ DT_N_S_pin_controller_P_compatible_IDX_0_EXISTS

#define DT_N_S_pin_controller_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_pin_controller_P_compatible_IDX_0_TOKEN

#define DT_N_S_pin_controller_P_compatible_IDX_0_TOKEN   nordic_nrf_pinctrl

◆ DT_N_S_pin_controller_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_pin_controller_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_PINCTRL

◆ DT_N_S_pin_controller_P_compatible_LEN

#define DT_N_S_pin_controller_P_compatible_LEN   1

◆ DT_N_S_pin_controller_P_wakeup_source

#define DT_N_S_pin_controller_P_wakeup_source   0

◆ DT_N_S_pin_controller_P_wakeup_source_EXISTS

#define DT_N_S_pin_controller_P_wakeup_source_EXISTS   1

◆ DT_N_S_pin_controller_PARENT

#define DT_N_S_pin_controller_PARENT   DT_N

◆ DT_N_S_pin_controller_PATH

#define DT_N_S_pin_controller_PATH   "/pin-controller"

◆ DT_N_S_pin_controller_PINCTRL_NUM

#define DT_N_S_pin_controller_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_RANGES_NUM

#define DT_N_S_pin_controller_RANGES_NUM   0

◆ DT_N_S_pin_controller_REG_NUM

#define DT_N_S_pin_controller_REG_NUM   0

◆ DT_N_S_pin_controller_REQUIRES_ORDS

#define DT_N_S_pin_controller_REQUIRES_ORDS    0, /* / */

◆ DT_N_S_pin_controller_S_i2c1_default_CHILD_IDX

#define DT_N_S_pin_controller_S_i2c1_default_CHILD_IDX   4

◆ DT_N_S_pin_controller_S_i2c1_default_EXISTS

#define DT_N_S_pin_controller_S_i2c1_default_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD

#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD (   fn)    fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)

◆ DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_pin_controller_S_i2c1_default_S_group1)

◆ DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_i2c1_default_FOREACH_RANGE

#define DT_N_S_pin_controller_S_i2c1_default_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_i2c1_default_FULL_NAME

#define DT_N_S_pin_controller_S_i2c1_default_FULL_NAME   "i2c1_default"

◆ DT_N_S_pin_controller_S_i2c1_default_IRQ_NUM

#define DT_N_S_pin_controller_S_i2c1_default_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_default_ORD

#define DT_N_S_pin_controller_S_i2c1_default_ORD   23

◆ DT_N_S_pin_controller_S_i2c1_default_PARENT

#define DT_N_S_pin_controller_S_i2c1_default_PARENT   DT_N_S_pin_controller

◆ DT_N_S_pin_controller_S_i2c1_default_PATH

#define DT_N_S_pin_controller_S_i2c1_default_PATH   "/pin-controller/i2c1_default"

◆ DT_N_S_pin_controller_S_i2c1_default_PINCTRL_NUM

#define DT_N_S_pin_controller_S_i2c1_default_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_default_RANGES_NUM

#define DT_N_S_pin_controller_S_i2c1_default_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_default_REG_NUM

#define DT_N_S_pin_controller_S_i2c1_default_REG_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_default_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_i2c1_default_REQUIRES_ORDS    22, /* /pin-controller */

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_CHILD_IDX

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_CHILD_IDX   0

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_EXISTS

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD (   fn)

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_RANGE

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_FULL_NAME

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_FULL_NAME   "group1"

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_IRQ_NUM

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_ORD

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_ORD   24

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_disable

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_disable   0

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_disable_EXISTS

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_disable_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_down

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_down   0

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_down_EXISTS

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_down_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_up

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_up   0

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_up_EXISTS

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_bias_pull_up_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_low_power_enable

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_low_power_enable   0

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_low_power_enable_EXISTS

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_low_power_enable_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_drive_mode

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_drive_mode   0

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_drive_mode_EXISTS

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_drive_mode_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_invert

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_invert   0

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_invert_EXISTS

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_nordic_invert_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels   {786440 /* 0xc0008 */, 720905 /* 0xb0009 */}

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_EXISTS

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 0) \
fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 1)

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 0, __VA_ARGS__) \
fn(DT_N_S_pin_controller_S_i2c1_default_S_group1, psels, 1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_0

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_0   786440

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_0_EXISTS

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_0_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_1

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_1   720905

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_1_EXISTS

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_IDX_1_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_LEN

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_P_psels_LEN   2

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_PARENT

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_PARENT   DT_N_S_pin_controller_S_i2c1_default

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_PATH

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_PATH   "/pin-controller/i2c1_default/group1"

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_PINCTRL_NUM

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_RANGES_NUM

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_REG_NUM

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_REG_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_REQUIRES_ORDS    23, /* /pin-controller/i2c1_default */

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_STATUS_okay

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_STATUS_okay   1

◆ DT_N_S_pin_controller_S_i2c1_default_S_group1_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_i2c1_default_S_group1_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_pin_controller_S_i2c1_default_STATUS_okay

#define DT_N_S_pin_controller_S_i2c1_default_STATUS_okay   1

◆ DT_N_S_pin_controller_S_i2c1_default_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_i2c1_default_SUPPORTS_ORDS
Value:
24, /* /pin-controller/i2c1_default/group1 */ \
56, /* /soc/peripheral@40000000/i2c@9000 */

◆ DT_N_S_pin_controller_S_i2c1_sleep_CHILD_IDX

#define DT_N_S_pin_controller_S_i2c1_sleep_CHILD_IDX   5

◆ DT_N_S_pin_controller_S_i2c1_sleep_EXISTS

#define DT_N_S_pin_controller_S_i2c1_sleep_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD

#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD (   fn)    fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1)

◆ DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1)

◆ DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_RANGE

#define DT_N_S_pin_controller_S_i2c1_sleep_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_i2c1_sleep_FULL_NAME

#define DT_N_S_pin_controller_S_i2c1_sleep_FULL_NAME   "i2c1_sleep"

◆ DT_N_S_pin_controller_S_i2c1_sleep_IRQ_NUM

#define DT_N_S_pin_controller_S_i2c1_sleep_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_sleep_ORD

#define DT_N_S_pin_controller_S_i2c1_sleep_ORD   25

◆ DT_N_S_pin_controller_S_i2c1_sleep_PARENT

#define DT_N_S_pin_controller_S_i2c1_sleep_PARENT   DT_N_S_pin_controller

◆ DT_N_S_pin_controller_S_i2c1_sleep_PATH

#define DT_N_S_pin_controller_S_i2c1_sleep_PATH   "/pin-controller/i2c1_sleep"

◆ DT_N_S_pin_controller_S_i2c1_sleep_PINCTRL_NUM

#define DT_N_S_pin_controller_S_i2c1_sleep_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_sleep_RANGES_NUM

#define DT_N_S_pin_controller_S_i2c1_sleep_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_sleep_REG_NUM

#define DT_N_S_pin_controller_S_i2c1_sleep_REG_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_sleep_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_i2c1_sleep_REQUIRES_ORDS    22, /* /pin-controller */

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_CHILD_IDX

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_CHILD_IDX   0

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_EXISTS

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD (   fn)

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_RANGE

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FULL_NAME

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_FULL_NAME   "group1"

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_IRQ_NUM

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_ORD

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_ORD   26

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_disable

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_disable   0

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_disable_EXISTS

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_disable_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_down

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_down   0

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_down_EXISTS

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_down_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_up

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_up   0

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_up_EXISTS

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_bias_pull_up_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_low_power_enable

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_low_power_enable   1

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_low_power_enable_EXISTS

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_low_power_enable_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_drive_mode

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_drive_mode   0

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_drive_mode_EXISTS

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_drive_mode_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_invert

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_invert   0

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_invert_EXISTS

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_nordic_invert_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels   {786440 /* 0xc0008 */, 720905 /* 0xb0009 */}

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_EXISTS

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 0) \
fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 1)

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 0, __VA_ARGS__) \
fn(DT_N_S_pin_controller_S_i2c1_sleep_S_group1, psels, 1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_0

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_0   786440

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_0_EXISTS

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_0_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_1

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_1   720905

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_1_EXISTS

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_IDX_1_EXISTS   1

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_LEN

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_P_psels_LEN   2

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PARENT

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PARENT   DT_N_S_pin_controller_S_i2c1_sleep

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PATH

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PATH   "/pin-controller/i2c1_sleep/group1"

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PINCTRL_NUM

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_RANGES_NUM

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_REG_NUM

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_REG_NUM   0

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_REQUIRES_ORDS    25, /* /pin-controller/i2c1_sleep */

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_STATUS_okay

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_STATUS_okay   1

◆ DT_N_S_pin_controller_S_i2c1_sleep_S_group1_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_i2c1_sleep_S_group1_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_pin_controller_S_i2c1_sleep_STATUS_okay

#define DT_N_S_pin_controller_S_i2c1_sleep_STATUS_okay   1

◆ DT_N_S_pin_controller_S_i2c1_sleep_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_i2c1_sleep_SUPPORTS_ORDS
Value:
26, /* /pin-controller/i2c1_sleep/group1 */ \
56, /* /soc/peripheral@40000000/i2c@9000 */

◆ DT_N_S_pin_controller_S_spi2_default_CHILD_IDX

#define DT_N_S_pin_controller_S_spi2_default_CHILD_IDX   6

◆ DT_N_S_pin_controller_S_spi2_default_EXISTS

#define DT_N_S_pin_controller_S_spi2_default_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD

#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD (   fn)    fn(DT_N_S_pin_controller_S_spi2_default_S_group1)

◆ DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_pin_controller_S_spi2_default_S_group1)

◆ DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_spi2_default_S_group1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_spi2_default_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_spi2_default_S_group1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_spi2_default_FOREACH_RANGE

#define DT_N_S_pin_controller_S_spi2_default_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_spi2_default_FULL_NAME

#define DT_N_S_pin_controller_S_spi2_default_FULL_NAME   "spi2_default"

◆ DT_N_S_pin_controller_S_spi2_default_IRQ_NUM

#define DT_N_S_pin_controller_S_spi2_default_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_spi2_default_ORD

#define DT_N_S_pin_controller_S_spi2_default_ORD   27

◆ DT_N_S_pin_controller_S_spi2_default_PARENT

#define DT_N_S_pin_controller_S_spi2_default_PARENT   DT_N_S_pin_controller

◆ DT_N_S_pin_controller_S_spi2_default_PATH

#define DT_N_S_pin_controller_S_spi2_default_PATH   "/pin-controller/spi2_default"

◆ DT_N_S_pin_controller_S_spi2_default_PINCTRL_NUM

#define DT_N_S_pin_controller_S_spi2_default_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_spi2_default_RANGES_NUM

#define DT_N_S_pin_controller_S_spi2_default_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_spi2_default_REG_NUM

#define DT_N_S_pin_controller_S_spi2_default_REG_NUM   0

◆ DT_N_S_pin_controller_S_spi2_default_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_spi2_default_REQUIRES_ORDS    22, /* /pin-controller */

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_CHILD_IDX

#define DT_N_S_pin_controller_S_spi2_default_S_group1_CHILD_IDX   0

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_EXISTS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD

#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD (   fn)

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_RANGE

#define DT_N_S_pin_controller_S_spi2_default_S_group1_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_FULL_NAME

#define DT_N_S_pin_controller_S_spi2_default_S_group1_FULL_NAME   "group1"

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_IRQ_NUM

#define DT_N_S_pin_controller_S_spi2_default_S_group1_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_ORD

#define DT_N_S_pin_controller_S_spi2_default_S_group1_ORD   28

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_disable

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_disable   0

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_disable_EXISTS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_disable_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_down

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_down   0

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_down_EXISTS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_down_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_up

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_up   0

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_up_EXISTS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_bias_pull_up_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_low_power_enable

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_low_power_enable   0

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_low_power_enable_EXISTS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_low_power_enable_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_drive_mode

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_drive_mode   0

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_drive_mode_EXISTS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_drive_mode_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_invert

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_invert   0

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_invert_EXISTS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_nordic_invert_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels   {262174 /* 0x4001e */, 393245 /* 0x6001d */, 327711 /* 0x5001f */}

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_EXISTS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_FOREACH_PROP_ELEM

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 0) \
fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 1) \
fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 2)

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 0, __VA_ARGS__) \
fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 1, __VA_ARGS__) \
fn(DT_N_S_pin_controller_S_spi2_default_S_group1, psels, 2, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_0

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_0   262174

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_0_EXISTS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_0_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_1

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_1   393245

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_1_EXISTS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_1_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_2

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_2   327711

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_2_EXISTS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_IDX_2_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_LEN

#define DT_N_S_pin_controller_S_spi2_default_S_group1_P_psels_LEN   3

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_PARENT

#define DT_N_S_pin_controller_S_spi2_default_S_group1_PARENT   DT_N_S_pin_controller_S_spi2_default

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_PATH

#define DT_N_S_pin_controller_S_spi2_default_S_group1_PATH   "/pin-controller/spi2_default/group1"

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_PINCTRL_NUM

#define DT_N_S_pin_controller_S_spi2_default_S_group1_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_RANGES_NUM

#define DT_N_S_pin_controller_S_spi2_default_S_group1_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_REG_NUM

#define DT_N_S_pin_controller_S_spi2_default_S_group1_REG_NUM   0

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_REQUIRES_ORDS    27, /* /pin-controller/spi2_default */

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_STATUS_okay

#define DT_N_S_pin_controller_S_spi2_default_S_group1_STATUS_okay   1

◆ DT_N_S_pin_controller_S_spi2_default_S_group1_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_spi2_default_S_group1_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_pin_controller_S_spi2_default_STATUS_okay

#define DT_N_S_pin_controller_S_spi2_default_STATUS_okay   1

◆ DT_N_S_pin_controller_S_spi2_default_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_spi2_default_SUPPORTS_ORDS
Value:
28, /* /pin-controller/spi2_default/group1 */ \
94, /* /soc/peripheral@40000000/spi@a000 */

◆ DT_N_S_pin_controller_S_spi2_sleep_CHILD_IDX

#define DT_N_S_pin_controller_S_spi2_sleep_CHILD_IDX   7

◆ DT_N_S_pin_controller_S_spi2_sleep_EXISTS

#define DT_N_S_pin_controller_S_spi2_sleep_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD

#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD (   fn)    fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1)

◆ DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1)

◆ DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_spi2_sleep_FOREACH_RANGE

#define DT_N_S_pin_controller_S_spi2_sleep_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_spi2_sleep_FULL_NAME

#define DT_N_S_pin_controller_S_spi2_sleep_FULL_NAME   "spi2_sleep"

◆ DT_N_S_pin_controller_S_spi2_sleep_IRQ_NUM

#define DT_N_S_pin_controller_S_spi2_sleep_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_spi2_sleep_ORD

#define DT_N_S_pin_controller_S_spi2_sleep_ORD   29

◆ DT_N_S_pin_controller_S_spi2_sleep_PARENT

#define DT_N_S_pin_controller_S_spi2_sleep_PARENT   DT_N_S_pin_controller

◆ DT_N_S_pin_controller_S_spi2_sleep_PATH

#define DT_N_S_pin_controller_S_spi2_sleep_PATH   "/pin-controller/spi2_sleep"

◆ DT_N_S_pin_controller_S_spi2_sleep_PINCTRL_NUM

#define DT_N_S_pin_controller_S_spi2_sleep_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_spi2_sleep_RANGES_NUM

#define DT_N_S_pin_controller_S_spi2_sleep_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_spi2_sleep_REG_NUM

#define DT_N_S_pin_controller_S_spi2_sleep_REG_NUM   0

◆ DT_N_S_pin_controller_S_spi2_sleep_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_spi2_sleep_REQUIRES_ORDS    22, /* /pin-controller */

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_CHILD_IDX

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_CHILD_IDX   0

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_EXISTS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD (   fn)

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_RANGE

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_FULL_NAME

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_FULL_NAME   "group1"

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_IRQ_NUM

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_ORD

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_ORD   30

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_disable

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_disable   0

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_disable_EXISTS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_disable_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_down

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_down   0

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_down_EXISTS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_down_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_up

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_up   0

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_up_EXISTS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_bias_pull_up_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_low_power_enable

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_low_power_enable   1

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_low_power_enable_EXISTS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_low_power_enable_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_drive_mode

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_drive_mode   0

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_drive_mode_EXISTS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_drive_mode_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_invert

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_invert   0

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_invert_EXISTS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_nordic_invert_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels   {262174 /* 0x4001e */, 393245 /* 0x6001d */, 327711 /* 0x5001f */}

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_EXISTS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 0) \
fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 1) \
fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 2)

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 0, __VA_ARGS__) \
fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 1, __VA_ARGS__) \
fn(DT_N_S_pin_controller_S_spi2_sleep_S_group1, psels, 2, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_0

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_0   262174

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_0_EXISTS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_0_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_1

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_1   393245

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_1_EXISTS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_1_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_2

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_2   327711

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_2_EXISTS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_IDX_2_EXISTS   1

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_LEN

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_P_psels_LEN   3

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_PARENT

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_PARENT   DT_N_S_pin_controller_S_spi2_sleep

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_PATH

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_PATH   "/pin-controller/spi2_sleep/group1"

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_PINCTRL_NUM

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_RANGES_NUM

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_REG_NUM

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_REG_NUM   0

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_REQUIRES_ORDS    29, /* /pin-controller/spi2_sleep */

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_STATUS_okay

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_STATUS_okay   1

◆ DT_N_S_pin_controller_S_spi2_sleep_S_group1_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_spi2_sleep_S_group1_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_pin_controller_S_spi2_sleep_STATUS_okay

#define DT_N_S_pin_controller_S_spi2_sleep_STATUS_okay   1

◆ DT_N_S_pin_controller_S_spi2_sleep_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_spi2_sleep_SUPPORTS_ORDS
Value:
30, /* /pin-controller/spi2_sleep/group1 */ \
94, /* /soc/peripheral@40000000/spi@a000 */

◆ DT_N_S_pin_controller_S_uart0_default_CHILD_IDX

#define DT_N_S_pin_controller_S_uart0_default_CHILD_IDX   0

◆ DT_N_S_pin_controller_S_uart0_default_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD

#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD (   fn)    fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2)

◆ DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_pin_controller_S_uart0_default_S_group1) fn(DT_N_S_pin_controller_S_uart0_default_S_group2)

◆ DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_uart0_default_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_uart0_default_S_group1, __VA_ARGS__) fn(DT_N_S_pin_controller_S_uart0_default_S_group2, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_uart0_default_FOREACH_RANGE

#define DT_N_S_pin_controller_S_uart0_default_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_uart0_default_FULL_NAME

#define DT_N_S_pin_controller_S_uart0_default_FULL_NAME   "uart0_default"

◆ DT_N_S_pin_controller_S_uart0_default_IRQ_NUM

#define DT_N_S_pin_controller_S_uart0_default_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_uart0_default_ORD

#define DT_N_S_pin_controller_S_uart0_default_ORD   31

◆ DT_N_S_pin_controller_S_uart0_default_PARENT

#define DT_N_S_pin_controller_S_uart0_default_PARENT   DT_N_S_pin_controller

◆ DT_N_S_pin_controller_S_uart0_default_PATH

#define DT_N_S_pin_controller_S_uart0_default_PATH   "/pin-controller/uart0_default"

◆ DT_N_S_pin_controller_S_uart0_default_PINCTRL_NUM

#define DT_N_S_pin_controller_S_uart0_default_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_uart0_default_RANGES_NUM

#define DT_N_S_pin_controller_S_uart0_default_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_uart0_default_REG_NUM

#define DT_N_S_pin_controller_S_uart0_default_REG_NUM   0

◆ DT_N_S_pin_controller_S_uart0_default_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_uart0_default_REQUIRES_ORDS    22, /* /pin-controller */

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_IDX

#define DT_N_S_pin_controller_S_uart0_default_S_group1_CHILD_IDX   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group1_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD

#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD (   fn)

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_RANGE

#define DT_N_S_pin_controller_S_uart0_default_S_group1_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_FULL_NAME

#define DT_N_S_pin_controller_S_uart0_default_S_group1_FULL_NAME   "group1"

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_IRQ_NUM

#define DT_N_S_pin_controller_S_uart0_default_S_group1_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_ORD

#define DT_N_S_pin_controller_S_uart0_default_S_group1_ORD   32

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_disable_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_down_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_bias_pull_up_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_low_power_enable_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_drive_mode_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_nordic_invert_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels   {6 /* 0x6 */}

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0)

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_uart0_default_S_group1, psels, 0, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0   6

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_IDX_0_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_LEN

#define DT_N_S_pin_controller_S_uart0_default_S_group1_P_psels_LEN   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_PARENT

#define DT_N_S_pin_controller_S_uart0_default_S_group1_PARENT   DT_N_S_pin_controller_S_uart0_default

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_PATH

#define DT_N_S_pin_controller_S_uart0_default_S_group1_PATH   "/pin-controller/uart0_default/group1"

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_PINCTRL_NUM

#define DT_N_S_pin_controller_S_uart0_default_S_group1_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_RANGES_NUM

#define DT_N_S_pin_controller_S_uart0_default_S_group1_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_REG_NUM

#define DT_N_S_pin_controller_S_uart0_default_S_group1_REG_NUM   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_uart0_default_S_group1_REQUIRES_ORDS    31, /* /pin-controller/uart0_default */

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_STATUS_okay

#define DT_N_S_pin_controller_S_uart0_default_S_group1_STATUS_okay   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group1_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_uart0_default_S_group1_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_IDX

#define DT_N_S_pin_controller_S_uart0_default_S_group2_CHILD_IDX   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group2_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD

#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD (   fn)

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_RANGE

#define DT_N_S_pin_controller_S_uart0_default_S_group2_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_FULL_NAME

#define DT_N_S_pin_controller_S_uart0_default_S_group2_FULL_NAME   "group2"

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_IRQ_NUM

#define DT_N_S_pin_controller_S_uart0_default_S_group2_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_ORD

#define DT_N_S_pin_controller_S_uart0_default_S_group2_ORD   33

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_disable_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_down_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_bias_pull_up_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_low_power_enable

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_low_power_enable   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_low_power_enable_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_low_power_enable_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_drive_mode

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_drive_mode   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_drive_mode_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_drive_mode_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_invert

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_invert   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_invert_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_nordic_invert_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels   {65543 /* 0x10007 */}

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0)

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_uart0_default_S_group2, psels, 0, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_0

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_0   65543

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_0_EXISTS

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_IDX_0_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_LEN

#define DT_N_S_pin_controller_S_uart0_default_S_group2_P_psels_LEN   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_PARENT

#define DT_N_S_pin_controller_S_uart0_default_S_group2_PARENT   DT_N_S_pin_controller_S_uart0_default

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_PATH

#define DT_N_S_pin_controller_S_uart0_default_S_group2_PATH   "/pin-controller/uart0_default/group2"

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_PINCTRL_NUM

#define DT_N_S_pin_controller_S_uart0_default_S_group2_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_RANGES_NUM

#define DT_N_S_pin_controller_S_uart0_default_S_group2_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_REG_NUM

#define DT_N_S_pin_controller_S_uart0_default_S_group2_REG_NUM   0

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_uart0_default_S_group2_REQUIRES_ORDS    31, /* /pin-controller/uart0_default */

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_STATUS_okay

#define DT_N_S_pin_controller_S_uart0_default_S_group2_STATUS_okay   1

◆ DT_N_S_pin_controller_S_uart0_default_S_group2_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_uart0_default_S_group2_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_pin_controller_S_uart0_default_STATUS_okay

#define DT_N_S_pin_controller_S_uart0_default_STATUS_okay   1

◆ DT_N_S_pin_controller_S_uart0_default_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_uart0_default_SUPPORTS_ORDS
Value:
32, /* /pin-controller/uart0_default/group1 */ \
33, /* /pin-controller/uart0_default/group2 */ \
77, /* /soc/peripheral@40000000/uart@8000 */

◆ DT_N_S_pin_controller_S_uart0_sleep_CHILD_IDX

#define DT_N_S_pin_controller_S_uart0_sleep_CHILD_IDX   1

◆ DT_N_S_pin_controller_S_uart0_sleep_EXISTS

#define DT_N_S_pin_controller_S_uart0_sleep_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD

#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD (   fn)    fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)

◆ DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1)

◆ DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_uart0_sleep_FOREACH_RANGE

#define DT_N_S_pin_controller_S_uart0_sleep_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_uart0_sleep_FULL_NAME

#define DT_N_S_pin_controller_S_uart0_sleep_FULL_NAME   "uart0_sleep"

◆ DT_N_S_pin_controller_S_uart0_sleep_IRQ_NUM

#define DT_N_S_pin_controller_S_uart0_sleep_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_uart0_sleep_ORD

#define DT_N_S_pin_controller_S_uart0_sleep_ORD   34

◆ DT_N_S_pin_controller_S_uart0_sleep_PARENT

#define DT_N_S_pin_controller_S_uart0_sleep_PARENT   DT_N_S_pin_controller

◆ DT_N_S_pin_controller_S_uart0_sleep_PATH

#define DT_N_S_pin_controller_S_uart0_sleep_PATH   "/pin-controller/uart0_sleep"

◆ DT_N_S_pin_controller_S_uart0_sleep_PINCTRL_NUM

#define DT_N_S_pin_controller_S_uart0_sleep_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_uart0_sleep_RANGES_NUM

#define DT_N_S_pin_controller_S_uart0_sleep_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_uart0_sleep_REG_NUM

#define DT_N_S_pin_controller_S_uart0_sleep_REG_NUM   0

◆ DT_N_S_pin_controller_S_uart0_sleep_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_uart0_sleep_REQUIRES_ORDS    22, /* /pin-controller */

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_CHILD_IDX

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_CHILD_IDX   0

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_EXISTS

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD (   fn)

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_RANGE

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_FULL_NAME

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_FULL_NAME   "group1"

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_IRQ_NUM

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_ORD

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_ORD   35

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable   0

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable_EXISTS

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_disable_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down   0

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down_EXISTS

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_down_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up   0

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up_EXISTS

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_bias_pull_up_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable   1

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable_EXISTS

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_low_power_enable_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode   0

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode_EXISTS

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_drive_mode_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert   0

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert_EXISTS

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_nordic_invert_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels   {6 /* 0x6 */, 65543 /* 0x10007 */}

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_EXISTS

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0) \
fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1)

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 0, __VA_ARGS__) \
fn(DT_N_S_pin_controller_S_uart0_sleep_S_group1, psels, 1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0   6

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0_EXISTS

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_0_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1   65543

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1_EXISTS

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_IDX_1_EXISTS   1

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_LEN

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_P_psels_LEN   2

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_PARENT

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PARENT   DT_N_S_pin_controller_S_uart0_sleep

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_PATH

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PATH   "/pin-controller/uart0_sleep/group1"

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_PINCTRL_NUM

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_RANGES_NUM

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_REG_NUM

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_REG_NUM   0

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_REQUIRES_ORDS    34, /* /pin-controller/uart0_sleep */

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_STATUS_okay

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_STATUS_okay   1

◆ DT_N_S_pin_controller_S_uart0_sleep_S_group1_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_uart0_sleep_S_group1_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_pin_controller_S_uart0_sleep_STATUS_okay

#define DT_N_S_pin_controller_S_uart0_sleep_STATUS_okay   1

◆ DT_N_S_pin_controller_S_uart0_sleep_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_uart0_sleep_SUPPORTS_ORDS
Value:
35, /* /pin-controller/uart0_sleep/group1 */ \
77, /* /soc/peripheral@40000000/uart@8000 */

◆ DT_N_S_pin_controller_S_uart2_default_CHILD_IDX

#define DT_N_S_pin_controller_S_uart2_default_CHILD_IDX   2

◆ DT_N_S_pin_controller_S_uart2_default_EXISTS

#define DT_N_S_pin_controller_S_uart2_default_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD

#define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD (   fn)    fn(DT_N_S_pin_controller_S_uart2_default_S_group1)

◆ DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_pin_controller_S_uart2_default_S_group1)

◆ DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_uart2_default_S_group1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_uart2_default_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_uart2_default_S_group1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_uart2_default_FOREACH_RANGE

#define DT_N_S_pin_controller_S_uart2_default_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_uart2_default_FULL_NAME

#define DT_N_S_pin_controller_S_uart2_default_FULL_NAME   "uart2_default"

◆ DT_N_S_pin_controller_S_uart2_default_IRQ_NUM

#define DT_N_S_pin_controller_S_uart2_default_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_uart2_default_ORD

#define DT_N_S_pin_controller_S_uart2_default_ORD   36

◆ DT_N_S_pin_controller_S_uart2_default_PARENT

#define DT_N_S_pin_controller_S_uart2_default_PARENT   DT_N_S_pin_controller

◆ DT_N_S_pin_controller_S_uart2_default_PATH

#define DT_N_S_pin_controller_S_uart2_default_PATH   "/pin-controller/uart2_default"

◆ DT_N_S_pin_controller_S_uart2_default_PINCTRL_NUM

#define DT_N_S_pin_controller_S_uart2_default_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_uart2_default_RANGES_NUM

#define DT_N_S_pin_controller_S_uart2_default_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_uart2_default_REG_NUM

#define DT_N_S_pin_controller_S_uart2_default_REG_NUM   0

◆ DT_N_S_pin_controller_S_uart2_default_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_uart2_default_REQUIRES_ORDS    22, /* /pin-controller */

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_CHILD_IDX

#define DT_N_S_pin_controller_S_uart2_default_S_group1_CHILD_IDX   0

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_EXISTS

#define DT_N_S_pin_controller_S_uart2_default_S_group1_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD

#define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD (   fn)

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_RANGE

#define DT_N_S_pin_controller_S_uart2_default_S_group1_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_FULL_NAME

#define DT_N_S_pin_controller_S_uart2_default_S_group1_FULL_NAME   "group1"

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_IRQ_NUM

#define DT_N_S_pin_controller_S_uart2_default_S_group1_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_ORD

#define DT_N_S_pin_controller_S_uart2_default_S_group1_ORD   37

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_disable

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_disable   0

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_disable_EXISTS

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_disable_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_down

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_down   0

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_down_EXISTS

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_down_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_up

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_up   0

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_up_EXISTS

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_bias_pull_up_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_low_power_enable

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_low_power_enable   0

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_low_power_enable_EXISTS

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_low_power_enable_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_drive_mode

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_drive_mode   0

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_drive_mode_EXISTS

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_drive_mode_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_invert

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_invert   0

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_invert_EXISTS

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_nordic_invert_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels   {24 /* 0x18 */, 65559 /* 0x10017 */}

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_EXISTS

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_FOREACH_PROP_ELEM

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_pin_controller_S_uart2_default_S_group1, psels, 0) \
fn(DT_N_S_pin_controller_S_uart2_default_S_group1, psels, 1)

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_pin_controller_S_uart2_default_S_group1, psels, 0, __VA_ARGS__) \
fn(DT_N_S_pin_controller_S_uart2_default_S_group1, psels, 1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_0

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_0   24

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_0_EXISTS

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_0_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_1

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_1   65559

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_1_EXISTS

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_IDX_1_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_LEN

#define DT_N_S_pin_controller_S_uart2_default_S_group1_P_psels_LEN   2

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_PARENT

#define DT_N_S_pin_controller_S_uart2_default_S_group1_PARENT   DT_N_S_pin_controller_S_uart2_default

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_PATH

#define DT_N_S_pin_controller_S_uart2_default_S_group1_PATH   "/pin-controller/uart2_default/group1"

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_PINCTRL_NUM

#define DT_N_S_pin_controller_S_uart2_default_S_group1_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_RANGES_NUM

#define DT_N_S_pin_controller_S_uart2_default_S_group1_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_REG_NUM

#define DT_N_S_pin_controller_S_uart2_default_S_group1_REG_NUM   0

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_uart2_default_S_group1_REQUIRES_ORDS    36, /* /pin-controller/uart2_default */

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_STATUS_okay

#define DT_N_S_pin_controller_S_uart2_default_S_group1_STATUS_okay   1

◆ DT_N_S_pin_controller_S_uart2_default_S_group1_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_uart2_default_S_group1_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_pin_controller_S_uart2_default_STATUS_okay

#define DT_N_S_pin_controller_S_uart2_default_STATUS_okay   1

◆ DT_N_S_pin_controller_S_uart2_default_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_uart2_default_SUPPORTS_ORDS
Value:
37, /* /pin-controller/uart2_default/group1 */ \
79, /* /soc/peripheral@40000000/uart@a000 */

◆ DT_N_S_pin_controller_S_uart2_sleep_CHILD_IDX

#define DT_N_S_pin_controller_S_uart2_sleep_CHILD_IDX   3

◆ DT_N_S_pin_controller_S_uart2_sleep_EXISTS

#define DT_N_S_pin_controller_S_uart2_sleep_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD

#define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD (   fn)    fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1)

◆ DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1)

◆ DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_uart2_sleep_FOREACH_RANGE

#define DT_N_S_pin_controller_S_uart2_sleep_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_uart2_sleep_FULL_NAME

#define DT_N_S_pin_controller_S_uart2_sleep_FULL_NAME   "uart2_sleep"

◆ DT_N_S_pin_controller_S_uart2_sleep_IRQ_NUM

#define DT_N_S_pin_controller_S_uart2_sleep_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_uart2_sleep_ORD

#define DT_N_S_pin_controller_S_uart2_sleep_ORD   38

◆ DT_N_S_pin_controller_S_uart2_sleep_PARENT

#define DT_N_S_pin_controller_S_uart2_sleep_PARENT   DT_N_S_pin_controller

◆ DT_N_S_pin_controller_S_uart2_sleep_PATH

#define DT_N_S_pin_controller_S_uart2_sleep_PATH   "/pin-controller/uart2_sleep"

◆ DT_N_S_pin_controller_S_uart2_sleep_PINCTRL_NUM

#define DT_N_S_pin_controller_S_uart2_sleep_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_uart2_sleep_RANGES_NUM

#define DT_N_S_pin_controller_S_uart2_sleep_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_uart2_sleep_REG_NUM

#define DT_N_S_pin_controller_S_uart2_sleep_REG_NUM   0

◆ DT_N_S_pin_controller_S_uart2_sleep_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_uart2_sleep_REQUIRES_ORDS    22, /* /pin-controller */

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_CHILD_IDX

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_CHILD_IDX   0

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_EXISTS

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD (   fn)

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_VARGS

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_RANGE

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FOREACH_RANGE (   fn)

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_FULL_NAME

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_FULL_NAME   "group1"

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_IRQ_NUM

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_IRQ_NUM   0

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_ORD

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_ORD   39

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_disable

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_disable   0

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_disable_EXISTS

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_disable_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_down

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_down   0

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_down_EXISTS

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_down_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_up

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_up   0

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_up_EXISTS

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_bias_pull_up_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_low_power_enable

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_low_power_enable   1

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_low_power_enable_EXISTS

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_low_power_enable_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_drive_mode

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_drive_mode   0

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_drive_mode_EXISTS

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_drive_mode_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_invert

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_invert   0

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_invert_EXISTS

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_nordic_invert_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels   {24 /* 0x18 */, 65559 /* 0x10017 */}

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_EXISTS

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 0) \
fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 1)

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 0, __VA_ARGS__) \
fn(DT_N_S_pin_controller_S_uart2_sleep_S_group1, psels, 1, __VA_ARGS__)

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_0

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_0   24

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_0_EXISTS

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_0_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_1

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_1   65559

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_1_EXISTS

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_IDX_1_EXISTS   1

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_LEN

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_P_psels_LEN   2

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_PARENT

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_PARENT   DT_N_S_pin_controller_S_uart2_sleep

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_PATH

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_PATH   "/pin-controller/uart2_sleep/group1"

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_PINCTRL_NUM

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_PINCTRL_NUM   0

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_RANGES_NUM

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_RANGES_NUM   0

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_REG_NUM

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_REG_NUM   0

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_REQUIRES_ORDS

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_REQUIRES_ORDS    38, /* /pin-controller/uart2_sleep */

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_STATUS_okay

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_STATUS_okay   1

◆ DT_N_S_pin_controller_S_uart2_sleep_S_group1_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_uart2_sleep_S_group1_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_pin_controller_S_uart2_sleep_STATUS_okay

#define DT_N_S_pin_controller_S_uart2_sleep_STATUS_okay   1

◆ DT_N_S_pin_controller_S_uart2_sleep_SUPPORTS_ORDS

#define DT_N_S_pin_controller_S_uart2_sleep_SUPPORTS_ORDS
Value:
39, /* /pin-controller/uart2_sleep/group1 */ \
79, /* /soc/peripheral@40000000/uart@a000 */

◆ DT_N_S_pin_controller_STATUS_okay

#define DT_N_S_pin_controller_STATUS_okay   1

◆ DT_N_S_pin_controller_SUPPORTS_ORDS

#define DT_N_S_pin_controller_SUPPORTS_ORDS
Value:
23, /* /pin-controller/i2c1_default */ \
25, /* /pin-controller/i2c1_sleep */ \
27, /* /pin-controller/spi2_default */ \
29, /* /pin-controller/spi2_sleep */ \
31, /* /pin-controller/uart0_default */ \
34, /* /pin-controller/uart0_sleep */ \
36, /* /pin-controller/uart2_default */ \
38, /* /pin-controller/uart2_sleep */

◆ DT_N_S_reserved_memory_CHILD_IDX

#define DT_N_S_reserved_memory_CHILD_IDX   9

◆ DT_N_S_reserved_memory_EXISTS

#define DT_N_S_reserved_memory_EXISTS   1

◆ DT_N_S_reserved_memory_FOREACH_CHILD

#define DT_N_S_reserved_memory_FOREACH_CHILD (   fn)    fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_modem_20016000) fn(DT_N_S_reserved_memory_S_image_ns_20020000)

◆ DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_reserved_memory_S_image_s_20000000) fn(DT_N_S_reserved_memory_S_image_modem_20016000) fn(DT_N_S_reserved_memory_S_image_ns_20020000)

◆ DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_reserved_memory_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_modem_20016000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20020000, __VA_ARGS__)

◆ DT_N_S_reserved_memory_FOREACH_CHILD_VARGS

#define DT_N_S_reserved_memory_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_reserved_memory_S_image_s_20000000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_modem_20016000, __VA_ARGS__) fn(DT_N_S_reserved_memory_S_image_ns_20020000, __VA_ARGS__)

◆ DT_N_S_reserved_memory_FOREACH_RANGE

#define DT_N_S_reserved_memory_FOREACH_RANGE (   fn)

◆ DT_N_S_reserved_memory_FULL_NAME

#define DT_N_S_reserved_memory_FULL_NAME   "reserved-memory"

◆ DT_N_S_reserved_memory_IRQ_NUM

#define DT_N_S_reserved_memory_IRQ_NUM   0

◆ DT_N_S_reserved_memory_ORD

#define DT_N_S_reserved_memory_ORD   40

◆ DT_N_S_reserved_memory_PARENT

#define DT_N_S_reserved_memory_PARENT   DT_N

◆ DT_N_S_reserved_memory_PATH

#define DT_N_S_reserved_memory_PATH   "/reserved-memory"

◆ DT_N_S_reserved_memory_PINCTRL_NUM

#define DT_N_S_reserved_memory_PINCTRL_NUM   0

◆ DT_N_S_reserved_memory_RANGES_NUM

#define DT_N_S_reserved_memory_RANGES_NUM   0

◆ DT_N_S_reserved_memory_REG_NUM

#define DT_N_S_reserved_memory_REG_NUM   0

◆ DT_N_S_reserved_memory_REQUIRES_ORDS

#define DT_N_S_reserved_memory_REQUIRES_ORDS    0, /* / */

◆ DT_N_S_reserved_memory_S_image_modem_20016000_CHILD_IDX

#define DT_N_S_reserved_memory_S_image_modem_20016000_CHILD_IDX   1

◆ DT_N_S_reserved_memory_S_image_modem_20016000_EXISTS

#define DT_N_S_reserved_memory_S_image_modem_20016000_EXISTS   1

◆ DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD

#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD (   fn)

◆ DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_VARGS

#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_RANGE

#define DT_N_S_reserved_memory_S_image_modem_20016000_FOREACH_RANGE (   fn)

◆ DT_N_S_reserved_memory_S_image_modem_20016000_FULL_NAME

#define DT_N_S_reserved_memory_S_image_modem_20016000_FULL_NAME   "image_modem@20016000"

◆ DT_N_S_reserved_memory_S_image_modem_20016000_IRQ_NUM

#define DT_N_S_reserved_memory_S_image_modem_20016000_IRQ_NUM   0

◆ DT_N_S_reserved_memory_S_image_modem_20016000_ORD

#define DT_N_S_reserved_memory_S_image_modem_20016000_ORD   41

◆ DT_N_S_reserved_memory_S_image_modem_20016000_P_reg

#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg   {536961024 /* 0x20016000 */, 40960 /* 0xa000 */}

◆ DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_EXISTS

#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_EXISTS   1

◆ DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_reserved_memory_S_image_modem_20016000, reg, 0) \
fn(DT_N_S_reserved_memory_S_image_modem_20016000, reg, 1)

◆ DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_reserved_memory_S_image_modem_20016000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_reserved_memory_S_image_modem_20016000, reg, 1, __VA_ARGS__)

◆ DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_0

#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_0   536961024

◆ DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_0_EXISTS

#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_1

#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_1   40960

◆ DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_1_EXISTS

#define DT_N_S_reserved_memory_S_image_modem_20016000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_reserved_memory_S_image_modem_20016000_PARENT

#define DT_N_S_reserved_memory_S_image_modem_20016000_PARENT   DT_N_S_reserved_memory

◆ DT_N_S_reserved_memory_S_image_modem_20016000_PATH

#define DT_N_S_reserved_memory_S_image_modem_20016000_PATH   "/reserved-memory/image_modem@20016000"

◆ DT_N_S_reserved_memory_S_image_modem_20016000_PINCTRL_NUM

#define DT_N_S_reserved_memory_S_image_modem_20016000_PINCTRL_NUM   0

◆ DT_N_S_reserved_memory_S_image_modem_20016000_RANGES_NUM

#define DT_N_S_reserved_memory_S_image_modem_20016000_RANGES_NUM   0

◆ DT_N_S_reserved_memory_S_image_modem_20016000_REG_IDX_0_EXISTS

#define DT_N_S_reserved_memory_S_image_modem_20016000_REG_IDX_0_EXISTS   1

◆ DT_N_S_reserved_memory_S_image_modem_20016000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_reserved_memory_S_image_modem_20016000_REG_IDX_0_VAL_ADDRESS   536961024 /* 0x20016000 */

◆ DT_N_S_reserved_memory_S_image_modem_20016000_REG_IDX_0_VAL_SIZE

#define DT_N_S_reserved_memory_S_image_modem_20016000_REG_IDX_0_VAL_SIZE   40960 /* 0xa000 */

◆ DT_N_S_reserved_memory_S_image_modem_20016000_REG_NUM

#define DT_N_S_reserved_memory_S_image_modem_20016000_REG_NUM   1

◆ DT_N_S_reserved_memory_S_image_modem_20016000_REQUIRES_ORDS

#define DT_N_S_reserved_memory_S_image_modem_20016000_REQUIRES_ORDS    40, /* /reserved-memory */

◆ DT_N_S_reserved_memory_S_image_modem_20016000_STATUS_okay

#define DT_N_S_reserved_memory_S_image_modem_20016000_STATUS_okay   1

◆ DT_N_S_reserved_memory_S_image_modem_20016000_SUPPORTS_ORDS

#define DT_N_S_reserved_memory_S_image_modem_20016000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_reserved_memory_S_image_ns_20020000_CHILD_IDX

#define DT_N_S_reserved_memory_S_image_ns_20020000_CHILD_IDX   2

◆ DT_N_S_reserved_memory_S_image_ns_20020000_EXISTS

#define DT_N_S_reserved_memory_S_image_ns_20020000_EXISTS   1

◆ DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD

#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD (   fn)

◆ DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_VARGS

#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_RANGE

#define DT_N_S_reserved_memory_S_image_ns_20020000_FOREACH_RANGE (   fn)

◆ DT_N_S_reserved_memory_S_image_ns_20020000_FULL_NAME

#define DT_N_S_reserved_memory_S_image_ns_20020000_FULL_NAME   "image_ns@20020000"

◆ DT_N_S_reserved_memory_S_image_ns_20020000_IRQ_NUM

#define DT_N_S_reserved_memory_S_image_ns_20020000_IRQ_NUM   0

◆ DT_N_S_reserved_memory_S_image_ns_20020000_ORD

#define DT_N_S_reserved_memory_S_image_ns_20020000_ORD   42

◆ DT_N_S_reserved_memory_S_image_ns_20020000_P_reg

#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg   {537001984 /* 0x20020000 */, 131072 /* 0x20000 */}

◆ DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_EXISTS

#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_EXISTS   1

◆ DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_reserved_memory_S_image_ns_20020000, reg, 0) \
fn(DT_N_S_reserved_memory_S_image_ns_20020000, reg, 1)

◆ DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_reserved_memory_S_image_ns_20020000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_reserved_memory_S_image_ns_20020000, reg, 1, __VA_ARGS__)

◆ DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_0

#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_0   537001984

◆ DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_0_EXISTS

#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_1

#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_1   131072

◆ DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_1_EXISTS

#define DT_N_S_reserved_memory_S_image_ns_20020000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_reserved_memory_S_image_ns_20020000_PARENT

#define DT_N_S_reserved_memory_S_image_ns_20020000_PARENT   DT_N_S_reserved_memory

◆ DT_N_S_reserved_memory_S_image_ns_20020000_PATH

#define DT_N_S_reserved_memory_S_image_ns_20020000_PATH   "/reserved-memory/image_ns@20020000"

◆ DT_N_S_reserved_memory_S_image_ns_20020000_PINCTRL_NUM

#define DT_N_S_reserved_memory_S_image_ns_20020000_PINCTRL_NUM   0

◆ DT_N_S_reserved_memory_S_image_ns_20020000_RANGES_NUM

#define DT_N_S_reserved_memory_S_image_ns_20020000_RANGES_NUM   0

◆ DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_EXISTS

#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_EXISTS   1

◆ DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_VAL_ADDRESS   537001984 /* 0x20020000 */

◆ DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_VAL_SIZE

#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_IDX_0_VAL_SIZE   131072 /* 0x20000 */

◆ DT_N_S_reserved_memory_S_image_ns_20020000_REG_NUM

#define DT_N_S_reserved_memory_S_image_ns_20020000_REG_NUM   1

◆ DT_N_S_reserved_memory_S_image_ns_20020000_REQUIRES_ORDS

#define DT_N_S_reserved_memory_S_image_ns_20020000_REQUIRES_ORDS    40, /* /reserved-memory */

◆ DT_N_S_reserved_memory_S_image_ns_20020000_STATUS_okay

#define DT_N_S_reserved_memory_S_image_ns_20020000_STATUS_okay   1

◆ DT_N_S_reserved_memory_S_image_ns_20020000_SUPPORTS_ORDS

#define DT_N_S_reserved_memory_S_image_ns_20020000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_reserved_memory_S_image_s_20000000_CHILD_IDX

#define DT_N_S_reserved_memory_S_image_s_20000000_CHILD_IDX   0

◆ DT_N_S_reserved_memory_S_image_s_20000000_EXISTS

#define DT_N_S_reserved_memory_S_image_s_20000000_EXISTS   1

◆ DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD

#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD (   fn)

◆ DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_VARGS

#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_RANGE

#define DT_N_S_reserved_memory_S_image_s_20000000_FOREACH_RANGE (   fn)

◆ DT_N_S_reserved_memory_S_image_s_20000000_FULL_NAME

#define DT_N_S_reserved_memory_S_image_s_20000000_FULL_NAME   "image_s@20000000"

◆ DT_N_S_reserved_memory_S_image_s_20000000_IRQ_NUM

#define DT_N_S_reserved_memory_S_image_s_20000000_IRQ_NUM   0

◆ DT_N_S_reserved_memory_S_image_s_20000000_ORD

#define DT_N_S_reserved_memory_S_image_s_20000000_ORD   43

◆ DT_N_S_reserved_memory_S_image_s_20000000_P_reg

#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg   {536870912 /* 0x20000000 */, 90112 /* 0x16000 */}

◆ DT_N_S_reserved_memory_S_image_s_20000000_P_reg_EXISTS

#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_EXISTS   1

◆ DT_N_S_reserved_memory_S_image_s_20000000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 0) \
fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 1)

◆ DT_N_S_reserved_memory_S_image_s_20000000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_reserved_memory_S_image_s_20000000, reg, 1, __VA_ARGS__)

◆ DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0

#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0   536870912

◆ DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0_EXISTS

#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1

#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1   90112

◆ DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1_EXISTS

#define DT_N_S_reserved_memory_S_image_s_20000000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_reserved_memory_S_image_s_20000000_PARENT

#define DT_N_S_reserved_memory_S_image_s_20000000_PARENT   DT_N_S_reserved_memory

◆ DT_N_S_reserved_memory_S_image_s_20000000_PATH

#define DT_N_S_reserved_memory_S_image_s_20000000_PATH   "/reserved-memory/image_s@20000000"

◆ DT_N_S_reserved_memory_S_image_s_20000000_PINCTRL_NUM

#define DT_N_S_reserved_memory_S_image_s_20000000_PINCTRL_NUM   0

◆ DT_N_S_reserved_memory_S_image_s_20000000_RANGES_NUM

#define DT_N_S_reserved_memory_S_image_s_20000000_RANGES_NUM   0

◆ DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_EXISTS

#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_EXISTS   1

◆ DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_ADDRESS   536870912 /* 0x20000000 */

◆ DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_SIZE

#define DT_N_S_reserved_memory_S_image_s_20000000_REG_IDX_0_VAL_SIZE   90112 /* 0x16000 */

◆ DT_N_S_reserved_memory_S_image_s_20000000_REG_NUM

#define DT_N_S_reserved_memory_S_image_s_20000000_REG_NUM   1

◆ DT_N_S_reserved_memory_S_image_s_20000000_REQUIRES_ORDS

#define DT_N_S_reserved_memory_S_image_s_20000000_REQUIRES_ORDS    40, /* /reserved-memory */

◆ DT_N_S_reserved_memory_S_image_s_20000000_STATUS_okay

#define DT_N_S_reserved_memory_S_image_s_20000000_STATUS_okay   1

◆ DT_N_S_reserved_memory_S_image_s_20000000_SUPPORTS_ORDS

#define DT_N_S_reserved_memory_S_image_s_20000000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_reserved_memory_STATUS_okay

#define DT_N_S_reserved_memory_STATUS_okay   1

◆ DT_N_S_reserved_memory_SUPPORTS_ORDS

#define DT_N_S_reserved_memory_SUPPORTS_ORDS
Value:
41, /* /reserved-memory/image_modem@20016000 */ \
42, /* /reserved-memory/image_ns@20020000 */ \
43, /* /reserved-memory/image_s@20000000 */

◆ DT_N_S_soc_CHILD_IDX

#define DT_N_S_soc_CHILD_IDX   2

◆ DT_N_S_soc_COMPAT_MATCHES_nordic_nrf91

#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf91   1

◆ DT_N_S_soc_COMPAT_MATCHES_nordic_nrf9160

#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf9160   1

◆ DT_N_S_soc_COMPAT_MATCHES_nordic_nrf9160_sica

#define DT_N_S_soc_COMPAT_MATCHES_nordic_nrf9160_sica   1

◆ DT_N_S_soc_COMPAT_MATCHES_simple_bus

#define DT_N_S_soc_COMPAT_MATCHES_simple_bus   1

◆ DT_N_S_soc_EXISTS

#define DT_N_S_soc_EXISTS   1

◆ DT_N_S_soc_FOREACH_CHILD

#define DT_N_S_soc_FOREACH_CHILD (   fn)    fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_40000000) fn(DT_N_S_soc_S_gpiote_40031000)

◆ DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_memory_20000000) fn(DT_N_S_soc_S_peripheral_40000000) fn(DT_N_S_soc_S_gpiote_40031000)

◆ DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_40031000, __VA_ARGS__)

◆ DT_N_S_soc_FOREACH_CHILD_VARGS

#define DT_N_S_soc_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_memory_20000000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_gpiote_40031000, __VA_ARGS__)

◆ DT_N_S_soc_FOREACH_RANGE

#define DT_N_S_soc_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_FULL_NAME

#define DT_N_S_soc_FULL_NAME   "soc"

◆ DT_N_S_soc_IRQ_NUM

#define DT_N_S_soc_IRQ_NUM   0

◆ DT_N_S_soc_ORD

#define DT_N_S_soc_ORD   5

◆ DT_N_S_soc_P_compatible

#define DT_N_S_soc_P_compatible   {"nordic,nRF9160-SICA", "nordic,nRF9160", "nordic,nRF91", "simple-bus"}

◆ DT_N_S_soc_P_compatible_EXISTS

#define DT_N_S_soc_P_compatible_EXISTS   1

◆ DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc, compatible, 0) \
fn(DT_N_S_soc, compatible, 1) \
fn(DT_N_S_soc, compatible, 2) \
fn(DT_N_S_soc, compatible, 3)

◆ DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc, compatible, 0, __VA_ARGS__) \
fn(DT_N_S_soc, compatible, 1, __VA_ARGS__) \
fn(DT_N_S_soc, compatible, 2, __VA_ARGS__) \
fn(DT_N_S_soc, compatible, 3, __VA_ARGS__)

◆ DT_N_S_soc_P_compatible_IDX_0

#define DT_N_S_soc_P_compatible_IDX_0   "nordic,nRF9160-SICA"

◆ DT_N_S_soc_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_P_compatible_IDX_0_TOKEN   nordic_nRF9160_SICA

◆ DT_N_S_soc_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF9160_SICA

◆ DT_N_S_soc_P_compatible_IDX_1

#define DT_N_S_soc_P_compatible_IDX_1   "nordic,nRF9160"

◆ DT_N_S_soc_P_compatible_IDX_1_EXISTS

#define DT_N_S_soc_P_compatible_IDX_1_EXISTS   1

◆ DT_N_S_soc_P_compatible_IDX_1_TOKEN

#define DT_N_S_soc_P_compatible_IDX_1_TOKEN   nordic_nRF9160

◆ DT_N_S_soc_P_compatible_IDX_1_UPPER_TOKEN

#define DT_N_S_soc_P_compatible_IDX_1_UPPER_TOKEN   NORDIC_NRF9160

◆ DT_N_S_soc_P_compatible_IDX_2

#define DT_N_S_soc_P_compatible_IDX_2   "nordic,nRF91"

◆ DT_N_S_soc_P_compatible_IDX_2_EXISTS

#define DT_N_S_soc_P_compatible_IDX_2_EXISTS   1

◆ DT_N_S_soc_P_compatible_IDX_2_TOKEN

#define DT_N_S_soc_P_compatible_IDX_2_TOKEN   nordic_nRF91

◆ DT_N_S_soc_P_compatible_IDX_2_UPPER_TOKEN

#define DT_N_S_soc_P_compatible_IDX_2_UPPER_TOKEN   NORDIC_NRF91

◆ DT_N_S_soc_P_compatible_IDX_3

#define DT_N_S_soc_P_compatible_IDX_3   "simple-bus"

◆ DT_N_S_soc_P_compatible_IDX_3_EXISTS

#define DT_N_S_soc_P_compatible_IDX_3_EXISTS   1

◆ DT_N_S_soc_P_compatible_IDX_3_TOKEN

#define DT_N_S_soc_P_compatible_IDX_3_TOKEN   simple_bus

◆ DT_N_S_soc_P_compatible_IDX_3_UPPER_TOKEN

#define DT_N_S_soc_P_compatible_IDX_3_UPPER_TOKEN   SIMPLE_BUS

◆ DT_N_S_soc_P_compatible_LEN

#define DT_N_S_soc_P_compatible_LEN   4

◆ DT_N_S_soc_PARENT

#define DT_N_S_soc_PARENT   DT_N

◆ DT_N_S_soc_PATH

#define DT_N_S_soc_PATH   "/soc"

◆ DT_N_S_soc_PINCTRL_NUM

#define DT_N_S_soc_PINCTRL_NUM   0

◆ DT_N_S_soc_RANGES_NUM

#define DT_N_S_soc_RANGES_NUM   0

◆ DT_N_S_soc_REG_NUM

#define DT_N_S_soc_REG_NUM   0

◆ DT_N_S_soc_REQUIRES_ORDS

#define DT_N_S_soc_REQUIRES_ORDS    0, /* / */

◆ DT_N_S_soc_S_gpiote_40031000_CHILD_IDX

#define DT_N_S_soc_S_gpiote_40031000_CHILD_IDX   4

◆ DT_N_S_soc_S_gpiote_40031000_COMPAT_MATCHES_nordic_nrf_gpiote

#define DT_N_S_soc_S_gpiote_40031000_COMPAT_MATCHES_nordic_nrf_gpiote   1

◆ DT_N_S_soc_S_gpiote_40031000_EXISTS

#define DT_N_S_soc_S_gpiote_40031000_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD

#define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_gpiote_40031000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_gpiote_40031000_FOREACH_RANGE

#define DT_N_S_soc_S_gpiote_40031000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_gpiote_40031000_FULL_NAME

#define DT_N_S_soc_S_gpiote_40031000_FULL_NAME   "gpiote@40031000"

◆ DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_irq   49

◆ DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_priority   5

◆ DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_gpiote_40031000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_IRQ_NUM

#define DT_N_S_soc_S_gpiote_40031000_IRQ_NUM   1

◆ DT_N_S_soc_S_gpiote_40031000_ORD

#define DT_N_S_soc_S_gpiote_40031000_ORD   44

◆ DT_N_S_soc_S_gpiote_40031000_P_compatible

#define DT_N_S_soc_S_gpiote_40031000_P_compatible   {"nordic,nrf-gpiote"}

◆ DT_N_S_soc_S_gpiote_40031000_P_compatible_EXISTS

#define DT_N_S_soc_S_gpiote_40031000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_gpiote_40031000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_gpiote_40031000, compatible, 0)

◆ DT_N_S_soc_S_gpiote_40031000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_gpiote_40031000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_gpiote_40031000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0

#define DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0   "nordic,nrf-gpiote"

◆ DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0_TOKEN   nordic_nrf_gpiote

◆ DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_gpiote_40031000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_GPIOTE

◆ DT_N_S_soc_S_gpiote_40031000_P_compatible_LEN

#define DT_N_S_soc_S_gpiote_40031000_P_compatible_LEN   1

◆ DT_N_S_soc_S_gpiote_40031000_P_interrupts

#define DT_N_S_soc_S_gpiote_40031000_P_interrupts   {49 /* 0x31 */, 5 /* 0x5 */}

◆ DT_N_S_soc_S_gpiote_40031000_P_interrupts_EXISTS

#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_gpiote_40031000, interrupts, 0) \
fn(DT_N_S_soc_S_gpiote_40031000, interrupts, 1)

◆ DT_N_S_soc_S_gpiote_40031000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_gpiote_40031000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_gpiote_40031000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_0

#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_0   49

◆ DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_1

#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_1   5

◆ DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_gpiote_40031000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_P_reg

#define DT_N_S_soc_S_gpiote_40031000_P_reg   {1073942528 /* 0x40031000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_gpiote_40031000_P_reg_EXISTS

#define DT_N_S_soc_S_gpiote_40031000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_gpiote_40031000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_gpiote_40031000, reg, 0) \
fn(DT_N_S_soc_S_gpiote_40031000, reg, 1)

◆ DT_N_S_soc_S_gpiote_40031000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_gpiote_40031000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_gpiote_40031000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_gpiote_40031000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_0

#define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_0   1073942528

◆ DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_1

#define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_gpiote_40031000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_P_status

#define DT_N_S_soc_S_gpiote_40031000_P_status   "okay"

◆ DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_IDX

#define DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_gpiote_40031000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_gpiote_40031000_P_status_EXISTS

#define DT_N_S_soc_S_gpiote_40031000_P_status_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_gpiote_40031000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_gpiote_40031000, status, 0) \
fn(DT_N_S_soc_S_gpiote_40031000, status, 1) \
fn(DT_N_S_soc_S_gpiote_40031000, status, 2) \
fn(DT_N_S_soc_S_gpiote_40031000, status, 3)

◆ DT_N_S_soc_S_gpiote_40031000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_gpiote_40031000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_gpiote_40031000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_gpiote_40031000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_gpiote_40031000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_gpiote_40031000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_gpiote_40031000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_gpiote_40031000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_gpiote_40031000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_gpiote_40031000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_gpiote_40031000_P_wakeup_source

#define DT_N_S_soc_S_gpiote_40031000_P_wakeup_source   0

◆ DT_N_S_soc_S_gpiote_40031000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_gpiote_40031000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_PARENT

#define DT_N_S_soc_S_gpiote_40031000_PARENT   DT_N_S_soc

◆ DT_N_S_soc_S_gpiote_40031000_PATH

#define DT_N_S_soc_S_gpiote_40031000_PATH   "/soc/gpiote@40031000"

◆ DT_N_S_soc_S_gpiote_40031000_PINCTRL_NUM

#define DT_N_S_soc_S_gpiote_40031000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_gpiote_40031000_RANGES_NUM

#define DT_N_S_soc_S_gpiote_40031000_RANGES_NUM   0

◆ DT_N_S_soc_S_gpiote_40031000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_gpiote_40031000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_gpiote_40031000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_gpiote_40031000_REG_IDX_0_VAL_ADDRESS   1073942528 /* 0x40031000 */

◆ DT_N_S_soc_S_gpiote_40031000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_gpiote_40031000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_gpiote_40031000_REG_NUM

#define DT_N_S_soc_S_gpiote_40031000_REG_NUM   1

◆ DT_N_S_soc_S_gpiote_40031000_REQUIRES_ORDS

#define DT_N_S_soc_S_gpiote_40031000_REQUIRES_ORDS
Value:
5, /* /soc */ \
6, /* /soc/interrupt-controller@e000e100 */

◆ DT_N_S_soc_S_gpiote_40031000_STATUS_okay

#define DT_N_S_soc_S_gpiote_40031000_STATUS_okay   1

◆ DT_N_S_soc_S_gpiote_40031000_SUPPORTS_ORDS

#define DT_N_S_soc_S_gpiote_40031000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_IDX

#define DT_N_S_soc_S_interrupt_controller_e000e100_CHILD_IDX   0

◆ DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MATCHES_arm_v8m_nvic

#define DT_N_S_soc_S_interrupt_controller_e000e100_COMPAT_MATCHES_arm_v8m_nvic   1

◆ DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS

#define DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS   1

◆ DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD

#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_RANGE

#define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME

#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME   "interrupt-controller@e000e100"

◆ DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_NUM

#define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_NUM   0

◆ DT_N_S_soc_S_interrupt_controller_e000e100_ORD

#define DT_N_S_soc_S_interrupt_controller_e000e100_ORD   6

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits   3

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS   1

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible   {"arm,v8m-nvic"}

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_EXISTS

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0)

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0   "arm,v8m-nvic"

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_TOKEN   arm_v8m_nvic

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_UPPER_TOKEN   ARM_V8M_NVIC

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_LEN

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_LEN   1

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller   1

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS   1

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_reg

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg   {3758153984 /* 0xe000e100 */, 3072 /* 0xc00 */}

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS   1

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 0) \
fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 1)

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_interrupt_controller_e000e100, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0   3758153984

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1   3072

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source   0

◆ DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_interrupt_controller_e000e100_PARENT

#define DT_N_S_soc_S_interrupt_controller_e000e100_PARENT   DT_N_S_soc

◆ DT_N_S_soc_S_interrupt_controller_e000e100_PATH

#define DT_N_S_soc_S_interrupt_controller_e000e100_PATH   "/soc/interrupt-controller@e000e100"

◆ DT_N_S_soc_S_interrupt_controller_e000e100_PINCTRL_NUM

#define DT_N_S_soc_S_interrupt_controller_e000e100_PINCTRL_NUM   0

◆ DT_N_S_soc_S_interrupt_controller_e000e100_RANGES_NUM

#define DT_N_S_soc_S_interrupt_controller_e000e100_RANGES_NUM   0

◆ DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS   3758153984 /* 0xe000e100 */

◆ DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE   3072 /* 0xc00 */

◆ DT_N_S_soc_S_interrupt_controller_e000e100_REG_NUM

#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_NUM   1

◆ DT_N_S_soc_S_interrupt_controller_e000e100_REQUIRES_ORDS

#define DT_N_S_soc_S_interrupt_controller_e000e100_REQUIRES_ORDS    5, /* /soc */

◆ DT_N_S_soc_S_interrupt_controller_e000e100_STATUS_okay

#define DT_N_S_soc_S_interrupt_controller_e000e100_STATUS_okay   1

◆ DT_N_S_soc_S_interrupt_controller_e000e100_SUPPORTS_ORDS

#define DT_N_S_soc_S_interrupt_controller_e000e100_SUPPORTS_ORDS

◆ DT_N_S_soc_S_memory_20000000_CHILD_IDX

#define DT_N_S_soc_S_memory_20000000_CHILD_IDX   2

◆ DT_N_S_soc_S_memory_20000000_COMPAT_MATCHES_mmio_sram

#define DT_N_S_soc_S_memory_20000000_COMPAT_MATCHES_mmio_sram   1

◆ DT_N_S_soc_S_memory_20000000_EXISTS

#define DT_N_S_soc_S_memory_20000000_EXISTS   1

◆ DT_N_S_soc_S_memory_20000000_FOREACH_CHILD

#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_memory_20000000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_memory_20000000_FOREACH_RANGE

#define DT_N_S_soc_S_memory_20000000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_memory_20000000_FULL_NAME

#define DT_N_S_soc_S_memory_20000000_FULL_NAME   "memory@20000000"

◆ DT_N_S_soc_S_memory_20000000_IRQ_NUM

#define DT_N_S_soc_S_memory_20000000_IRQ_NUM   0

◆ DT_N_S_soc_S_memory_20000000_ORD

#define DT_N_S_soc_S_memory_20000000_ORD   45

◆ DT_N_S_soc_S_memory_20000000_P_compatible

#define DT_N_S_soc_S_memory_20000000_P_compatible   {"mmio-sram"}

◆ DT_N_S_soc_S_memory_20000000_P_compatible_EXISTS

#define DT_N_S_soc_S_memory_20000000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_memory_20000000, compatible, 0)

◆ DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_memory_20000000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_memory_20000000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0

#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0   "mmio-sram"

◆ DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_TOKEN   mmio_sram

◆ DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_memory_20000000_P_compatible_IDX_0_UPPER_TOKEN   MMIO_SRAM

◆ DT_N_S_soc_S_memory_20000000_P_compatible_LEN

#define DT_N_S_soc_S_memory_20000000_P_compatible_LEN   1

◆ DT_N_S_soc_S_memory_20000000_P_reg

#define DT_N_S_soc_S_memory_20000000_P_reg   {536870912 /* 0x20000000 */, 262144 /* 0x40000 */}

◆ DT_N_S_soc_S_memory_20000000_P_reg_EXISTS

#define DT_N_S_soc_S_memory_20000000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_memory_20000000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_memory_20000000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_memory_20000000, reg, 0) \
fn(DT_N_S_soc_S_memory_20000000, reg, 1)

◆ DT_N_S_soc_S_memory_20000000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_memory_20000000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_memory_20000000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_memory_20000000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_memory_20000000_P_reg_IDX_0

#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0   536870912

◆ DT_N_S_soc_S_memory_20000000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_memory_20000000_P_reg_IDX_1

#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1   262144

◆ DT_N_S_soc_S_memory_20000000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_memory_20000000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_memory_20000000_P_wakeup_source

#define DT_N_S_soc_S_memory_20000000_P_wakeup_source   0

◆ DT_N_S_soc_S_memory_20000000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_memory_20000000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_memory_20000000_PARENT

#define DT_N_S_soc_S_memory_20000000_PARENT   DT_N_S_soc

◆ DT_N_S_soc_S_memory_20000000_PATH

#define DT_N_S_soc_S_memory_20000000_PATH   "/soc/memory@20000000"

◆ DT_N_S_soc_S_memory_20000000_PINCTRL_NUM

#define DT_N_S_soc_S_memory_20000000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_memory_20000000_RANGES_NUM

#define DT_N_S_soc_S_memory_20000000_RANGES_NUM   0

◆ DT_N_S_soc_S_memory_20000000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_ADDRESS   536870912 /* 0x20000000 */

◆ DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_memory_20000000_REG_IDX_0_VAL_SIZE   262144 /* 0x40000 */

◆ DT_N_S_soc_S_memory_20000000_REG_NUM

#define DT_N_S_soc_S_memory_20000000_REG_NUM   1

◆ DT_N_S_soc_S_memory_20000000_REQUIRES_ORDS

#define DT_N_S_soc_S_memory_20000000_REQUIRES_ORDS    5, /* /soc */

◆ DT_N_S_soc_S_memory_20000000_STATUS_okay

#define DT_N_S_soc_S_memory_20000000_STATUS_okay   1

◆ DT_N_S_soc_S_memory_20000000_SUPPORTS_ORDS

#define DT_N_S_soc_S_memory_20000000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_CHILD_IDX   3

◆ DT_N_S_soc_S_peripheral_40000000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000) fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000)

◆ DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000) fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000) fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000) fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000) fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000)

◆ DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_FOREACH_RANGE (   fn)    fn(DT_N_S_soc_S_peripheral_40000000, 0)

◆ DT_N_S_soc_S_peripheral_40000000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_FULL_NAME   "peripheral@40000000"

◆ DT_N_S_soc_S_peripheral_40000000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_ORD

#define DT_N_S_soc_S_peripheral_40000000_ORD   7

◆ DT_N_S_soc_S_peripheral_40000000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_PARENT   DT_N_S_soc

◆ DT_N_S_soc_S_peripheral_40000000_PATH

#define DT_N_S_soc_S_peripheral_40000000_PATH   "/soc/peripheral@40000000"

◆ DT_N_S_soc_S_peripheral_40000000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_VAL_CHILD_BUS_ADDRESS   0 /* 0x0 */

◆ DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_VAL_LENGTH

#define DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_VAL_LENGTH   268435456 /* 0x10000000 */

◆ DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_RANGES_IDX_0_VAL_PARENT_BUS_ADDRESS   1073741824 /* 0x40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_RANGES_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_REG_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_REQUIRES_ORDS    5, /* /soc */

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_CHILD_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_COMPAT_MATCHES_nordic_nrf_saadc

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_COMPAT_MATCHES_nordic_nrf_saadc   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_CHILD (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_FULL_NAME   "adc@e000"

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_irq   14

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_ORD   8

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible   {"nordic,nrf-saadc"}

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_IDX_0   "nordic,nrf-saadc"

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_IDX_0_TOKEN   nordic_nrf_saadc

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_SAADC

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts   {14 /* 0xe */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_0   14

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg   {57344 /* 0xe000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_0   57344

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_PATH   "/soc/peripheral@40000000/adc@e000"

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_IDX_0_VAL_ADDRESS   1073799168 /* 0x4000e000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_CHILD_IDX   0

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_FULL_NAME   "channel@0"

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_ORD   83

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg   {0 /* 0x0 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, reg, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, reg, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg_IDX_0   0

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_acquisition_time

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_acquisition_time   0

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_acquisition_time_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_acquisition_time_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain   "ADC_GAIN_1_5"

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_ENUM_TOKEN   ADC_GAIN_1_5

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_ENUM_UPPER_TOKEN   ADC_GAIN_1_5

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 7) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 8) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 9) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 10) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 11)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 7, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 8, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 9, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 10, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_gain, 11, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_STRING_TOKEN   ADC_GAIN_1_5

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_gain_STRING_UPPER_TOKEN   ADC_GAIN_1_5

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_input_positive

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_input_positive   4

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_input_positive_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_input_positive_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference   "ADC_REF_INTERNAL"

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_ENUM_IDX   4

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_ENUM_TOKEN   ADC_REF_INTERNAL

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_ENUM_UPPER_TOKEN   ADC_REF_INTERNAL

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 7) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 8) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 9) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 10) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 11) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 12) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 13) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 14) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 15)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 7, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 8, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 9, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 10, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 11, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 12, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 13, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 14, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0, zephyr_reference, 15, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_STRING_TOKEN   ADC_REF_INTERNAL

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_reference_STRING_UPPER_TOKEN   ADC_REF_INTERNAL

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_resolution

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_resolution   12

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_resolution_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_P_zephyr_resolution_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_PARENT   DT_N_S_soc_S_peripheral_40000000_S_adc_e000

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_PATH   "/soc/peripheral@40000000/adc@e000/channel@0"

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_REG_IDX_0_VAL_ADDRESS   0 /* 0x0 */

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_REQUIRES_ORDS    8, /* /soc/peripheral@40000000/adc@e000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_S_channel_0_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_adc_e000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_adc_e000_SUPPORTS_ORDS
Value:
10, /* /zephyr,user */ \
83, /* /soc/peripheral@40000000/adc@e000/channel@0 */

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_CHILD_IDX   34

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_COMPAT_MATCHES_nordic_nrf_clock

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_COMPAT_MATCHES_nordic_nrf_clock   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_FULL_NAME   "clock@5000"

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_irq   5

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_ORD   47

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible   {"nordic,nrf-clock"}

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_IDX_0   "nordic,nrf-clock"

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_IDX_0_TOKEN   nordic_nrf_clock

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_CLOCK

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts   {5 /* 0x5 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_0   5

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg   {20480 /* 0x5000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_0   20480

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_clock_5000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_PATH   "/soc/peripheral@40000000/clock@5000"

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_IDX_0_VAL_ADDRESS   1073762304 /* 0x40005000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_clock_5000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_clock_5000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_CHILD_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_COMPAT_MATCHES_nordic_nrf_dppic

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_COMPAT_MATCHES_nordic_nrf_dppic   1

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_FULL_NAME   "dppic@17000"

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_ORD   48

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible   {"nordic,nrf-dppic"}

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_IDX_0   "nordic,nrf-dppic"

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_IDX_0_TOKEN   nordic_nrf_dppic

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_DPPIC

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg   {94208 /* 0x17000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_0   94208

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_dppic_17000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_PATH   "/soc/peripheral@40000000/dppic@17000"

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_IDX_0_VAL_ADDRESS   1073836032 /* 0x40017000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_REQUIRES_ORDS    7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_dppic_17000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_CHILD_IDX   3

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_COMPAT_MATCHES_nordic_nrf_egu

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_COMPAT_MATCHES_nordic_nrf_egu   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_FULL_NAME   "egu@1b000"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_irq   27

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_ORD   49

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible   {"nordic,nrf-egu"}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_IDX_0   "nordic,nrf-egu"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_IDX_0_TOKEN   nordic_nrf_egu

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_EGU

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts   {27 /* 0x1b */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_0   27

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg   {110592 /* 0x1b000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_0   110592

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1b000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_PATH   "/soc/peripheral@40000000/egu@1b000"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_IDX_0_VAL_ADDRESS   1073852416 /* 0x4001b000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1b000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_CHILD_IDX   4

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_COMPAT_MATCHES_nordic_nrf_egu

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_COMPAT_MATCHES_nordic_nrf_egu   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_FULL_NAME   "egu@1c000"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_irq   28

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_ORD   50

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible   {"nordic,nrf-egu"}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_IDX_0   "nordic,nrf-egu"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_IDX_0_TOKEN   nordic_nrf_egu

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_EGU

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts   {28 /* 0x1c */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_0   28

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg   {114688 /* 0x1c000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_0   114688

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1c000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_PATH   "/soc/peripheral@40000000/egu@1c000"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_IDX_0_VAL_ADDRESS   1073856512 /* 0x4001c000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1c000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_CHILD_IDX   5

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_COMPAT_MATCHES_nordic_nrf_egu

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_COMPAT_MATCHES_nordic_nrf_egu   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_FULL_NAME   "egu@1d000"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_irq   29

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_ORD   51

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible   {"nordic,nrf-egu"}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_IDX_0   "nordic,nrf-egu"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_IDX_0_TOKEN   nordic_nrf_egu

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_EGU

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts   {29 /* 0x1d */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_0   29

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg   {118784 /* 0x1d000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_0   118784

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1d000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_PATH   "/soc/peripheral@40000000/egu@1d000"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_IDX_0_VAL_ADDRESS   1073860608 /* 0x4001d000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1d000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_CHILD_IDX   6

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_COMPAT_MATCHES_nordic_nrf_egu

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_COMPAT_MATCHES_nordic_nrf_egu   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_FULL_NAME   "egu@1e000"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_irq   30

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_ORD   52

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible   {"nordic,nrf-egu"}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_IDX_0   "nordic,nrf-egu"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_IDX_0_TOKEN   nordic_nrf_egu

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_EGU

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts   {30 /* 0x1e */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_0   30

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg   {122880 /* 0x1e000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_0   122880

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1e000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_PATH   "/soc/peripheral@40000000/egu@1e000"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_IDX_0_VAL_ADDRESS   1073864704 /* 0x4001e000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1e000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_CHILD_IDX   7

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_COMPAT_MATCHES_nordic_nrf_egu

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_COMPAT_MATCHES_nordic_nrf_egu   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_FULL_NAME   "egu@1f000"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_irq   31

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_ORD   53

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible   {"nordic,nrf-egu"}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_IDX_0   "nordic,nrf-egu"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_IDX_0_TOKEN   nordic_nrf_egu

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_EGU

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts   {31 /* 0x1f */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_0   31

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg   {126976 /* 0x1f000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_0   126976

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_1f000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_PATH   "/soc/peripheral@40000000/egu@1f000"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_IDX_0_VAL_ADDRESS   1073868800 /* 0x4001f000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_1f000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_CHILD_IDX   8

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_COMPAT_MATCHES_nordic_nrf_egu

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_COMPAT_MATCHES_nordic_nrf_egu   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_FULL_NAME   "egu@20000"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_irq   32

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_ORD   54

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible   {"nordic,nrf-egu"}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_IDX_0   "nordic,nrf-egu"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_IDX_0_TOKEN   nordic_nrf_egu

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_EGU

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts   {32 /* 0x20 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_0   32

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg   {131072 /* 0x20000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_0   131072

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_egu_20000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_PATH   "/soc/peripheral@40000000/egu@20000"

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_IDX_0_VAL_ADDRESS   1073872896 /* 0x40020000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_egu_20000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_egu_20000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_CHILD_IDX   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_COMPAT_MATCHES_nordic_nrf91_flash_controller

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_COMPAT_MATCHES_nordic_nrf91_flash_controller   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_CHILD (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_FULL_NAME   "flash-controller@39000"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_ORD   84

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible   {"nordic,nrf91-flash-controller"}

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_IDX_0   "nordic,nrf91-flash-controller"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_IDX_0_TOKEN   nordic_nrf91_flash_controller

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF91_FLASH_CONTROLLER

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_partial_erase

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_partial_erase   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_partial_erase_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_partial_erase_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg   {233472 /* 0x39000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_0   233472

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_PATH   "/soc/peripheral@40000000/flash-controller@39000"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_IDX_0_VAL_ADDRESS   1073975296 /* 0x40039000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_REQUIRES_ORDS    7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_CHILD_IDX   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_COMPAT_MATCHES_soc_nv_flash

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_COMPAT_MATCHES_soc_nv_flash   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_FULL_NAME   "flash@0"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_ORD   85

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible   {"soc-nv-flash"}

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0   "soc-nv-flash"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_TOKEN   soc_nv_flash

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_IDX_0_UPPER_TOKEN   SOC_NV_FLASH

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_erase_block_size

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_erase_block_size   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_erase_block_size_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_erase_block_size_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg   {0 /* 0x0 */, 1048576 /* 0x100000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1   1048576

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_write_block_size

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_write_block_size   4

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_write_block_size_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_P_write_block_size_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_ADDRESS   0 /* 0x0 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_IDX_0_VAL_SIZE   1048576 /* 0x100000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_REQUIRES_ORDS    84, /* /soc/peripheral@40000000/flash-controller@39000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_CHILD_IDX   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_COMPAT_MATCHES_fixed_partitions

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_COMPAT_MATCHES_fixed_partitions   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, __VA_ARGS__) fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_FULL_NAME   "partitions"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_ORD   86

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_REG_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_REQUIRES_ORDS    85, /* /soc/peripheral@40000000/flash-controller@39000/flash@0 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_CHILD_IDX   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_FULL_NAME   "partition@0"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_ORD   87

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label   "mcuboot"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 6)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, label, 6, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_TOKEN   mcuboot

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_label_STRING_UPPER_TOKEN   MCUBOOT

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_read_only_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg   {0 /* 0x0 */, 65536 /* 0x10000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1   65536

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARTITION_ID

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PARTITION_ID   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@0"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS   0 /* 0x0 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE   65536 /* 0x10000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_REQUIRES_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_0_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_CHILD_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_FULL_NAME   "partition@10000"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_ORD   88

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label   "image-0"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 6)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, label, 6, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_TOKEN   image_0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_label_STRING_UPPER_TOKEN   IMAGE_0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_read_only_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg   {65536 /* 0x10000 */, 262144 /* 0x40000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0   65536

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1   262144

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARTITION_ID

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PARTITION_ID   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@10000"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_ADDRESS   65536 /* 0x10000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_IDX_0_VAL_SIZE   262144 /* 0x40000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_REQUIRES_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_10000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_CHILD_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_FULL_NAME   "partition@50000"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_ORD   89

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label   "image-0-nonsecure"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 7) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 8) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 9) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 10) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 11) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 12) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 13) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 14) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 15) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 16)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 7, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 8, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 9, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 10, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 11, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 12, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 13, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 14, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 15, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, label, 16, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_TOKEN   image_0_nonsecure

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_label_STRING_UPPER_TOKEN   IMAGE_0_NONSECURE

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_read_only_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg   {327680 /* 0x50000 */, 196608 /* 0x30000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0   327680

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1   196608

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARTITION_ID

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PARTITION_ID   2

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@50000"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_ADDRESS   327680 /* 0x50000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_IDX_0_VAL_SIZE   196608 /* 0x30000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_REQUIRES_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_50000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_CHILD_IDX   3

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_FULL_NAME   "partition@80000"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_ORD   90

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label   "image-1"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 6)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, label, 6, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_STRING_TOKEN   image_1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_label_STRING_UPPER_TOKEN   IMAGE_1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_read_only_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg   {524288 /* 0x80000 */, 262144 /* 0x40000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_0   524288

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_1   262144

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARTITION_ID

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PARTITION_ID   3

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@80000"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_ADDRESS   524288 /* 0x80000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_IDX_0_VAL_SIZE   262144 /* 0x40000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_REQUIRES_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_80000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_CHILD_IDX   4

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_FULL_NAME   "partition@c0000"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_ORD   91

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label   "image-1-nonsecure"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 7) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 8) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 9) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 10) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 11) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 12) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 13) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 14) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 15) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 16)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 7, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 8, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 9, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 10, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 11, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 12, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 13, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 14, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 15, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, label, 16, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_STRING_TOKEN   image_1_nonsecure

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_label_STRING_UPPER_TOKEN   IMAGE_1_NONSECURE

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_read_only

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_read_only   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_read_only_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_read_only_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg   {786432 /* 0xc0000 */, 196608 /* 0x30000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_0   786432

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_1   196608

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PARTITION_ID

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PARTITION_ID   4

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@c0000"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_VAL_ADDRESS   786432 /* 0xc0000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_IDX_0_VAL_SIZE   196608 /* 0x30000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_REQUIRES_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_c0000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_CHILD_IDX   5

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_FULL_NAME   "partition@f0000"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_ORD   92

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label   "image-scratch"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 7) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 8) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 9) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 10) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 11) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 12)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 7, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 8, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 9, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 10, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 11, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, label, 12, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_STRING_TOKEN   image_scratch

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_label_STRING_UPPER_TOKEN   IMAGE_SCRATCH

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_read_only

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_read_only   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_read_only_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_read_only_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg   {983040 /* 0xf0000 */, 40960 /* 0xa000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_0   983040

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_1   40960

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PARTITION_ID

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PARTITION_ID   5

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@f0000"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_VAL_ADDRESS   983040 /* 0xf0000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_IDX_0_VAL_SIZE   40960 /* 0xa000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_REQUIRES_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_f0000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_CHILD_IDX   6

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_FULL_NAME   "partition@fa000"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_ORD   93

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label   "storage"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 6)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, label, 6, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_STRING_TOKEN   storage

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_label_STRING_UPPER_TOKEN   STORAGE

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_read_only

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_read_only   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_read_only_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_read_only_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg   {1024000 /* 0xfa000 */, 24576 /* 0x6000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_0   1024000

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_1   24576

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PARENT   DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PARTITION_ID

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PARTITION_ID   6

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PATH   "/soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@fa000"

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_VAL_ADDRESS   1024000 /* 0xfa000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_IDX_0_VAL_SIZE   24576 /* 0x6000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_REQUIRES_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_S_partition_fa000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_S_partitions_SUPPORTS_ORDS
Value:
87, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@0 */ \
88, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@10000 */ \
89, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@50000 */ \
90, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@80000 */ \
91, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@c0000 */ \
92, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@f0000 */ \
93, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions/partition@fa000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_S_flash_0_SUPPORTS_ORDS    86, /* /soc/peripheral@40000000/flash-controller@39000/flash@0/partitions */

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_flash_controller_39000_SUPPORTS_ORDS    85, /* /soc/peripheral@40000000/flash-controller@39000/flash@0 */

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_CHILD_IDX   31

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_COMPAT_MATCHES_nordic_nrf_gpio

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_COMPAT_MATCHES_nordic_nrf_gpio   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_FULL_NAME   "gpio@842500"

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_ORD   9

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible   {"nordic,nrf-gpio"}

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_IDX_0   "nordic,nrf-gpio"

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_IDX_0_TOKEN   nordic_nrf_gpio

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_GPIO

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_gpio_controller

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_gpio_controller   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_gpio_controller_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_gpio_controller_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_ngpios

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_ngpios   32

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_ngpios_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_ngpios_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_port

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_port   0

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_port_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_port_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg   {8660224 /* 0x842500 */, 768 /* 0x300 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_0   8660224

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_1   768

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_gpio_842500, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_PATH   "/soc/peripheral@40000000/gpio@842500"

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_IDX_0_VAL_ADDRESS   1082402048 /* 0x40842500 */

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_IDX_0_VAL_SIZE   768 /* 0x300 */

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_REQUIRES_ORDS    7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_gpio_842500_SUPPORTS_ORDS
Value:
10, /* /zephyr,user */ \
12, /* /buttons/button_0 */ \
13, /* /buttons/button_1 */ \
14, /* /buttons/button_2 */ \
19, /* /leds/led_0 */ \
20, /* /leds/led_1 */ \
21, /* /leds/led_2 */ \
94, /* /soc/peripheral@40000000/spi@a000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_CHILD_IDX   19

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_COMPAT_MATCHES_nordic_nrf_twim

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_COMPAT_MATCHES_nordic_nrf_twim   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_FULL_NAME   "i2c@8000"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_irq   8

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_ORD   55

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_clock_frequency

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_clock_frequency   100000

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_clock_frequency_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_clock_frequency_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible   {"nordic,nrf-twim"}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_IDX_0   "nordic,nrf-twim"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_IDX_0_TOKEN   nordic_nrf_twim

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_TWIM

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts   {8 /* 0x8 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_0   8

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg   {32768 /* 0x8000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_0   32768

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status   "disabled"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 7)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_8000, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_zephyr_concat_buf_size

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_zephyr_concat_buf_size   16

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_zephyr_concat_buf_size_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_zephyr_concat_buf_size_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_zephyr_flash_buf_max_size

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_zephyr_flash_buf_max_size   16

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_zephyr_flash_buf_max_size_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_P_zephyr_flash_buf_max_size_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_PATH   "/soc/peripheral@40000000/i2c@8000"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_IDX_0_VAL_ADDRESS   1073774592 /* 0x40008000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_STATUS_disabled

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_STATUS_disabled   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_8000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_CHILD_IDX   20

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_COMPAT_MATCHES_nordic_nrf_twim

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_COMPAT_MATCHES_nordic_nrf_twim   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_FULL_NAME   "i2c@9000"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_irq   9

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_ORD   56

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_clock_frequency

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_clock_frequency   100000

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_clock_frequency_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_clock_frequency_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible   {"nordic,nrf-twim"}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_IDX_0   "nordic,nrf-twim"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_IDX_0_TOKEN   nordic_nrf_twim

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_TWIM

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts   {9 /* 0x9 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_0   9

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, pinctrl_0, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, pinctrl_0, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_IDX_0   DT_N_S_pin_controller_S_i2c1_default

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_IDX_0_PH   DT_N_S_pin_controller_S_i2c1_default

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_0_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, pinctrl_1, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, pinctrl_1, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_IDX_0   DT_N_S_pin_controller_S_i2c1_sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_IDX_0_PH   DT_N_S_pin_controller_S_i2c1_sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_1_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names   {"default", "sleep"}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, pinctrl_names, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, pinctrl_names, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, pinctrl_names, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, pinctrl_names, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_0   "default"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_0_TOKEN   default

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_0_UPPER_TOKEN   DEFAULT

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_1   "sleep"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_1_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_1_TOKEN   sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_1_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_IDX_1_UPPER_TOKEN   SLEEP

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_pinctrl_names_LEN   2

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg   {36864 /* 0x9000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_0   36864

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_9000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_zephyr_concat_buf_size

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_zephyr_concat_buf_size   16

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_zephyr_concat_buf_size_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_zephyr_concat_buf_size_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_zephyr_flash_buf_max_size

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_zephyr_flash_buf_max_size   16

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_zephyr_flash_buf_max_size_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_P_zephyr_flash_buf_max_size_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PATH   "/soc/peripheral@40000000/i2c@9000"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_0_TOKEN   default

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_0_UPPER_TOKEN   DEFAULT

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_1_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_1_TOKEN   sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_1_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_IDX_1_UPPER_TOKEN   SLEEP

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_default_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_default_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_default_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_default_IDX   0

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_default_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_default_IDX_0_PH   DT_N_S_pin_controller_S_i2c1_default

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_sleep_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_sleep_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_sleep_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_sleep_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_sleep_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NAME_sleep_IDX_0_PH   DT_N_S_pin_controller_S_i2c1_sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_PINCTRL_NUM   2

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_IDX_0_VAL_ADDRESS   1073778688 /* 0x40009000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */ \
23, /* /pin-controller/i2c1_default */ \
25, /* /pin-controller/i2c1_sleep */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_9000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_CHILD_IDX   21

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_COMPAT_MATCHES_nordic_nrf_twim

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_COMPAT_MATCHES_nordic_nrf_twim   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_FULL_NAME   "i2c@a000"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_irq   10

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_ORD   57

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_clock_frequency

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_clock_frequency   100000

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_clock_frequency_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_clock_frequency_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible   {"nordic,nrf-twim"}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_IDX_0   "nordic,nrf-twim"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_IDX_0_TOKEN   nordic_nrf_twim

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_TWIM

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts   {10 /* 0xa */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_0   10

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg   {40960 /* 0xa000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_0   40960

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status   "disabled"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 7)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_a000, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_zephyr_concat_buf_size

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_zephyr_concat_buf_size   16

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_zephyr_concat_buf_size_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_zephyr_concat_buf_size_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_zephyr_flash_buf_max_size

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_zephyr_flash_buf_max_size   16

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_zephyr_flash_buf_max_size_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_P_zephyr_flash_buf_max_size_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_PATH   "/soc/peripheral@40000000/i2c@a000"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_IDX_0_VAL_ADDRESS   1073782784 /* 0x4000a000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_STATUS_disabled

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_STATUS_disabled   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_a000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_CHILD_IDX   22

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_COMPAT_MATCHES_nordic_nrf_twim

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_COMPAT_MATCHES_nordic_nrf_twim   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_FULL_NAME   "i2c@b000"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_irq   11

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_ORD   58

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_clock_frequency

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_clock_frequency   100000

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_clock_frequency_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_clock_frequency_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible   {"nordic,nrf-twim"}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_IDX_0   "nordic,nrf-twim"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_IDX_0_TOKEN   nordic_nrf_twim

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_TWIM

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts   {11 /* 0xb */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_0   11

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg   {45056 /* 0xb000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_0   45056

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status   "disabled"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 7)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2c_b000, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_zephyr_concat_buf_size

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_zephyr_concat_buf_size   16

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_zephyr_concat_buf_size_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_zephyr_concat_buf_size_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_zephyr_flash_buf_max_size

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_zephyr_flash_buf_max_size   16

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_zephyr_flash_buf_max_size_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_P_zephyr_flash_buf_max_size_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_PATH   "/soc/peripheral@40000000/i2c@b000"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_IDX_0_VAL_ADDRESS   1073786880 /* 0x4000b000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_STATUS_disabled

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_STATUS_disabled   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_i2c_b000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_CHILD_IDX   10

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_COMPAT_MATCHES_nordic_nrf_i2s

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_COMPAT_MATCHES_nordic_nrf_i2s   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_FULL_NAME   "i2s@28000"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_irq   40

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_ORD   59

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source   "PCLK32M_HFXO"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_ENUM_TOKEN   PCLK32M_HFXO

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_ENUM_UPPER_TOKEN   PCLK32M_HFXO

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 7) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 8) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 9) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 10) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 11)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 7, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 8, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 9, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 10, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, clock_source, 11, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_STRING_TOKEN   PCLK32M_HFXO

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_clock_source_STRING_UPPER_TOKEN   PCLK32M_HFXO

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible   {"nordic,nrf-i2s"}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_IDX_0   "nordic,nrf-i2s"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_IDX_0_TOKEN   nordic_nrf_i2s

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_I2S

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts   {40 /* 0x28 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_0   40

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg   {163840 /* 0x28000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_0   163840

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status   "disabled"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 7)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_i2s_28000, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_PATH   "/soc/peripheral@40000000/i2s@28000"

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_IDX_0_VAL_ADDRESS   1073905664 /* 0x40028000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_STATUS_disabled

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_STATUS_disabled   1

◆ DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_i2s_28000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_CHILD_IDX   9

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_COMPAT_MATCHES_nordic_nrf_ipc

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_COMPAT_MATCHES_nordic_nrf_ipc   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_FULL_NAME   "ipc@2a000"

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_VAL_irq   42

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_ORD   60

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible   {"nordic,nrf-ipc"}

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_IDX_0   "nordic,nrf-ipc"

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_IDX_0_TOKEN   nordic_nrf_ipc

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_IPC

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts   {42 /* 0x2a */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_IDX_0   42

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg   {172032 /* 0x2a000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_IDX_0   172032

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_PATH   "/soc/peripheral@40000000/ipc@2a000"

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_REG_IDX_0_VAL_ADDRESS   1073913856 /* 0x4002a000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_ipc_2a000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_CHILD_IDX   11

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_COMPAT_MATCHES_nordic_nrf_kmu

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_COMPAT_MATCHES_nordic_nrf_kmu   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_FULL_NAME   "kmu@39000"

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_irq   57

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_ORD   61

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible   {"nordic,nrf-kmu"}

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_IDX_0   "nordic,nrf-kmu"

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_IDX_0_TOKEN   nordic_nrf_kmu

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_KMU

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts   {57 /* 0x39 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_0   57

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg   {233472 /* 0x39000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_0   233472

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_kmu_39000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_PATH   "/soc/peripheral@40000000/kmu@39000"

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_IDX_0_VAL_ADDRESS   1073975296 /* 0x40039000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_kmu_39000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_CHILD_IDX   12

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_COMPAT_MATCHES_nordic_nrf_pdm

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_COMPAT_MATCHES_nordic_nrf_pdm   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_FULL_NAME   "pdm@26000"

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_irq   38

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_ORD   62

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source   "PCLK32M_HFXO"

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_ENUM_TOKEN   PCLK32M_HFXO

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_ENUM_UPPER_TOKEN   PCLK32M_HFXO

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 7) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 8) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 9) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 10) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 11)

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 7, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 8, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 9, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 10, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, clock_source, 11, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_STRING_TOKEN   PCLK32M_HFXO

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_clock_source_STRING_UPPER_TOKEN   PCLK32M_HFXO

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible   {"nordic,nrf-pdm"}

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_IDX_0   "nordic,nrf-pdm"

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_IDX_0_TOKEN   nordic_nrf_pdm

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_PDM

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts   {38 /* 0x26 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_0   38

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_queue_size

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_queue_size   4

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_queue_size_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_queue_size_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg   {155648 /* 0x26000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_0   155648

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status   "disabled"

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 7)

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pdm_26000, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_PATH   "/soc/peripheral@40000000/pdm@26000"

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_IDX_0_VAL_ADDRESS   1073897472 /* 0x40026000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_STATUS_disabled

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_STATUS_disabled   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_pdm_26000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_CHILD_IDX   35

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_COMPAT_MATCHES_nordic_nrf_power

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_COMPAT_MATCHES_nordic_nrf_power   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_FULL_NAME   "power@5000"

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_irq   5

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_ORD   63

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible   {"nordic,nrf-power"}

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_IDX_0   "nordic,nrf-power"

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_IDX_0_TOKEN   nordic_nrf_power

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_POWER

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts   {5 /* 0x5 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_0   5

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg   {20480 /* 0x5000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_0   20480

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_power_5000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_PATH   "/soc/peripheral@40000000/power@5000"

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_IDX_0_VAL_ADDRESS   1073762304 /* 0x40005000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_power_5000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_power_5000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_CHILD_IDX   27

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_COMPAT_MATCHES_nordic_nrf_pwm

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_COMPAT_MATCHES_nordic_nrf_pwm   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_FULL_NAME   "pwm@21000"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_irq   33

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_ORD   64

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_center_aligned

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_center_aligned   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_center_aligned_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_center_aligned_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch0_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch0_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch0_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch0_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch1_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch1_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch1_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch1_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch2_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch2_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch2_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch2_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch3_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch3_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch3_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_ch3_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible   {"nordic,nrf-pwm"}

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_IDX_0   "nordic,nrf-pwm"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_IDX_0_TOKEN   nordic_nrf_pwm

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_PWM

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts   {33 /* 0x21 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_0   33

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg   {135168 /* 0x21000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_0   135168

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status   "disabled"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 7)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_21000, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_PATH   "/soc/peripheral@40000000/pwm@21000"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_IDX_0_VAL_ADDRESS   1073876992 /* 0x40021000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_STATUS_disabled

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_STATUS_disabled   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_21000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_CHILD_IDX   28

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_COMPAT_MATCHES_nordic_nrf_pwm

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_COMPAT_MATCHES_nordic_nrf_pwm   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_FULL_NAME   "pwm@22000"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_irq   34

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_ORD   65

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_center_aligned

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_center_aligned   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_center_aligned_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_center_aligned_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch0_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch0_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch0_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch0_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch1_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch1_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch1_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch1_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch2_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch2_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch2_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch2_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch3_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch3_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch3_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_ch3_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible   {"nordic,nrf-pwm"}

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_IDX_0   "nordic,nrf-pwm"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_IDX_0_TOKEN   nordic_nrf_pwm

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_PWM

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts   {34 /* 0x22 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_0   34

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg   {139264 /* 0x22000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_0   139264

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status   "disabled"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 7)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_22000, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_PATH   "/soc/peripheral@40000000/pwm@22000"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_IDX_0_VAL_ADDRESS   1073881088 /* 0x40022000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_STATUS_disabled

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_STATUS_disabled   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_22000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_CHILD_IDX   29

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_COMPAT_MATCHES_nordic_nrf_pwm

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_COMPAT_MATCHES_nordic_nrf_pwm   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_FULL_NAME   "pwm@23000"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_irq   35

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_ORD   66

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_center_aligned

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_center_aligned   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_center_aligned_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_center_aligned_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch0_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch0_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch0_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch0_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch1_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch1_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch1_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch1_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch2_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch2_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch2_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch2_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch3_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch3_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch3_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_ch3_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible   {"nordic,nrf-pwm"}

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_IDX_0   "nordic,nrf-pwm"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_IDX_0_TOKEN   nordic_nrf_pwm

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_PWM

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts   {35 /* 0x23 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_0   35

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg   {143360 /* 0x23000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_0   143360

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status   "disabled"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 7)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_23000, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_PATH   "/soc/peripheral@40000000/pwm@23000"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_IDX_0_VAL_ADDRESS   1073885184 /* 0x40023000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_STATUS_disabled

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_STATUS_disabled   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_23000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_CHILD_IDX   30

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_COMPAT_MATCHES_nordic_nrf_pwm

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_COMPAT_MATCHES_nordic_nrf_pwm   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_FULL_NAME   "pwm@24000"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_irq   36

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_ORD   67

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_center_aligned

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_center_aligned   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_center_aligned_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_center_aligned_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch0_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch0_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch0_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch0_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch1_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch1_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch1_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch1_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch2_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch2_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch2_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch2_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch3_inverted

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch3_inverted   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch3_inverted_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_ch3_inverted_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible   {"nordic,nrf-pwm"}

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_IDX_0   "nordic,nrf-pwm"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_IDX_0_TOKEN   nordic_nrf_pwm

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_PWM

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts   {36 /* 0x24 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_0   36

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg   {147456 /* 0x24000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_0   147456

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status   "disabled"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 7)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_pwm_24000, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_PATH   "/soc/peripheral@40000000/pwm@24000"

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_IDX_0_VAL_ADDRESS   1073889280 /* 0x40024000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_STATUS_disabled

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_STATUS_disabled   1

◆ DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_pwm_24000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_CHILD_IDX   13

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_COMPAT_MATCHES_nordic_nrf_regulators

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_COMPAT_MATCHES_nordic_nrf_regulators   1

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_FULL_NAME   "regulator@4000"

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_ORD   68

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible   {"nordic,nrf-regulators"}

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_IDX_0   "nordic,nrf-regulators"

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_IDX_0_TOKEN   nordic_nrf_regulators

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_REGULATORS

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg   {16384 /* 0x4000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_0   16384

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_regulator_4000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_PATH   "/soc/peripheral@40000000/regulator@4000"

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_IDX_0_VAL_ADDRESS   1073758208 /* 0x40004000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_REQUIRES_ORDS    7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_regulator_4000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_CHILD_IDX   32

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_COMPAT_MATCHES_nordic_nrf_rtc

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_COMPAT_MATCHES_nordic_nrf_rtc   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_FULL_NAME   "rtc@14000"

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_irq   20

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_ORD   69

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_cc_num

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_cc_num   4

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_cc_num_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_cc_num_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_clock_frequency

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_clock_frequency   32768

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_clock_frequency_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_clock_frequency_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible   {"nordic,nrf-rtc"}

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_IDX_0   "nordic,nrf-rtc"

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_IDX_0_TOKEN   nordic_nrf_rtc

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_RTC

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_fixed_top

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_fixed_top   0

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_fixed_top_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_fixed_top_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts   {20 /* 0x14 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_0   20

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_ppi_wrap

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_ppi_wrap   0

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_ppi_wrap_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_ppi_wrap_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_prescaler

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_prescaler   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_prescaler_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_prescaler_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg   {81920 /* 0x14000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_0   81920

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_14000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_PATH   "/soc/peripheral@40000000/rtc@14000"

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_IDX_0_VAL_ADDRESS   1073823744 /* 0x40014000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_14000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_CHILD_IDX   33

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_COMPAT_MATCHES_nordic_nrf_rtc

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_COMPAT_MATCHES_nordic_nrf_rtc   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_FULL_NAME   "rtc@15000"

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_irq   21

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_ORD   70

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_cc_num

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_cc_num   4

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_cc_num_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_cc_num_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_clock_frequency

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_clock_frequency   32768

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_clock_frequency_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_clock_frequency_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible   {"nordic,nrf-rtc"}

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_IDX_0   "nordic,nrf-rtc"

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_IDX_0_TOKEN   nordic_nrf_rtc

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_RTC

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_fixed_top

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_fixed_top   0

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_fixed_top_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_fixed_top_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts   {21 /* 0x15 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_0   21

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_ppi_wrap

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_ppi_wrap   0

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_ppi_wrap_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_ppi_wrap_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_prescaler

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_prescaler   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_prescaler_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_prescaler_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg   {86016 /* 0x15000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_0   86016

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_rtc_15000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_PATH   "/soc/peripheral@40000000/rtc@15000"

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_IDX_0_VAL_ADDRESS   1073827840 /* 0x40015000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_rtc_15000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_CHILD_IDX   23

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_COMPAT_MATCHES_nordic_nrf_spim

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_COMPAT_MATCHES_nordic_nrf_spim   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_FULL_NAME   "spi@8000"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_irq   8

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_ORD   71

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_anomaly_58_workaround

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_anomaly_58_workaround   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_anomaly_58_workaround_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_anomaly_58_workaround_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible   {"nordic,nrf-spim"}

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_IDX_0   "nordic,nrf-spim"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_IDX_0_TOKEN   nordic_nrf_spim

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_SPIM

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts   {8 /* 0x8 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_0   8

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_max_frequency

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_max_frequency   8000000

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_max_frequency_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_max_frequency_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_miso_pull_down

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_miso_pull_down   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_miso_pull_down_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_miso_pull_down_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_miso_pull_up

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_miso_pull_up   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_miso_pull_up_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_miso_pull_up_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_overrun_character

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_overrun_character   255

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_overrun_character_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_overrun_character_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg   {32768 /* 0x8000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_0   32768

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_rx_delay_supported

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_rx_delay_supported   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_rx_delay_supported_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_rx_delay_supported_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status   "disabled"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 7)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_8000, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_PATH   "/soc/peripheral@40000000/spi@8000"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_IDX_0_VAL_ADDRESS   1073774592 /* 0x40008000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_STATUS_disabled

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_STATUS_disabled   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_8000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_8000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_CHILD_IDX   24

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_COMPAT_MATCHES_nordic_nrf_spim

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_COMPAT_MATCHES_nordic_nrf_spim   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_FULL_NAME   "spi@9000"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_irq   9

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_ORD   72

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_anomaly_58_workaround

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_anomaly_58_workaround   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_anomaly_58_workaround_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_anomaly_58_workaround_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible   {"nordic,nrf-spim"}

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_IDX_0   "nordic,nrf-spim"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_IDX_0_TOKEN   nordic_nrf_spim

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_SPIM

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts   {9 /* 0x9 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_0   9

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_max_frequency

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_max_frequency   8000000

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_max_frequency_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_max_frequency_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_miso_pull_down

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_miso_pull_down   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_miso_pull_down_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_miso_pull_down_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_miso_pull_up

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_miso_pull_up   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_miso_pull_up_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_miso_pull_up_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_overrun_character

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_overrun_character   255

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_overrun_character_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_overrun_character_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg   {36864 /* 0x9000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_0   36864

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_rx_delay_supported

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_rx_delay_supported   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_rx_delay_supported_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_rx_delay_supported_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status   "disabled"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 7)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_9000, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_PATH   "/soc/peripheral@40000000/spi@9000"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_IDX_0_VAL_ADDRESS   1073778688 /* 0x40009000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_STATUS_disabled

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_STATUS_disabled   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_9000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_9000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_CHILD_IDX   25

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_COMPAT_MATCHES_nordic_nrf_spim

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_COMPAT_MATCHES_nordic_nrf_spim   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_CHILD (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_CHILD_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_FULL_NAME   "spi@a000"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_irq   10

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_ORD   94

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_anomaly_58_workaround

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_anomaly_58_workaround   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_anomaly_58_workaround_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_anomaly_58_workaround_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible   {"nordic,nrf-spim"}

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_IDX_0   "nordic,nrf-spim"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_IDX_0_TOKEN   nordic_nrf_spim

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_SPIM

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, cs_gpios, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, cs_gpios, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, cs_gpios, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, cs_gpios, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_flags

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_flags   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_pin

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_pin   28

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_PH

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_VAL_flags

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_VAL_flags   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_VAL_flags_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_VAL_flags_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_VAL_pin

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_VAL_pin   20

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_VAL_pin_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_IDX_1_VAL_pin_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_cs_gpios_LEN   2

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts   {10 /* 0xa */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_0   10

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_max_frequency

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_max_frequency   8000000

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_max_frequency_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_max_frequency_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_miso_pull_down

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_miso_pull_down   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_miso_pull_down_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_miso_pull_down_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_miso_pull_up

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_miso_pull_up   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_miso_pull_up_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_miso_pull_up_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_overrun_character

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_overrun_character   255

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_overrun_character_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_overrun_character_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, pinctrl_0, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, pinctrl_0, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_IDX_0   DT_N_S_pin_controller_S_spi2_default

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_IDX_0_PH   DT_N_S_pin_controller_S_spi2_default

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_0_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, pinctrl_1, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, pinctrl_1, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_IDX_0   DT_N_S_pin_controller_S_spi2_sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_IDX_0_PH   DT_N_S_pin_controller_S_spi2_sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_1_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names   {"default", "sleep"}

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, pinctrl_names, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, pinctrl_names, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, pinctrl_names, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, pinctrl_names, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_0   "default"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_0_TOKEN   default

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_0_UPPER_TOKEN   DEFAULT

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_1   "sleep"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_1_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_1_TOKEN   sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_1_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_IDX_1_UPPER_TOKEN   SLEEP

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_pinctrl_names_LEN   2

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg   {40960 /* 0xa000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_0   40960

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_rx_delay_supported

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_rx_delay_supported   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_rx_delay_supported_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_rx_delay_supported_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PATH   "/soc/peripheral@40000000/spi@a000"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_0_TOKEN   default

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_0_UPPER_TOKEN   DEFAULT

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_1_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_1_TOKEN   sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_1_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_IDX_1_UPPER_TOKEN   SLEEP

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_default_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_default_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_default_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_default_IDX   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_default_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_default_IDX_0_PH   DT_N_S_pin_controller_S_spi2_default

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_sleep_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_sleep_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_sleep_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_sleep_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_sleep_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NAME_sleep_IDX_0_PH   DT_N_S_pin_controller_S_spi2_sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_PINCTRL_NUM   2

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_IDX_0_VAL_ADDRESS   1073782784 /* 0x4000a000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */ \
9, /* /soc/peripheral@40000000/gpio@842500 */ \
27, /* /pin-controller/spi2_default */ \
29, /* /pin-controller/spi2_sleep */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_BUS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_BUS   DT_N_S_soc_S_peripheral_40000000_S_spi_a000

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_BUS_spi

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_BUS_spi   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_CHILD_IDX   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_COMPAT_MATCHES_sharp_ls0xx

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_COMPAT_MATCHES_sharp_ls0xx   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_FULL_NAME   "ls0xx@0"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_ORD   95

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible   {"sharp,ls0xx"}

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_IDX_0   "sharp,ls0xx"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_IDX_0_TOKEN   sharp_ls0xx

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_IDX_0_UPPER_TOKEN   SHARP_LS0XX

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_duplex

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_duplex   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_duplex_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_duplex_ENUM_IDX   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_duplex_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_duplex_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_frame_format

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_frame_format   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_frame_format_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_frame_format_ENUM_IDX   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_frame_format_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_frame_format_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_height

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_height   68

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_height_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_height_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label   "DISPLAY"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, label, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, label, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, label, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, label, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, label, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, label, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, label, 6)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, label, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, label, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, label, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, label, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, label, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, label, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, label, 6, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label_STRING_TOKEN   DISPLAY

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_label_STRING_UPPER_TOKEN   DISPLAY

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg   {0 /* 0x0 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, reg, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0, reg, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg_IDX_0   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_spi_max_frequency

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_spi_max_frequency   2000000

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_spi_max_frequency_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_spi_max_frequency_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_width

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_width   160

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_width_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_P_width_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_PARENT   DT_N_S_soc_S_peripheral_40000000_S_spi_a000

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_PATH   "/soc/peripheral@40000000/spi@a000/ls0xx@0"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_REG_IDX_0_VAL_ADDRESS   0 /* 0x0 */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_REQUIRES_ORDS    94, /* /soc/peripheral@40000000/spi@a000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_S_ls0xx_0_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_a000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_a000_SUPPORTS_ORDS    95, /* /soc/peripheral@40000000/spi@a000/ls0xx@0 */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_CHILD_IDX   26

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_COMPAT_MATCHES_nordic_nrf_spim

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_COMPAT_MATCHES_nordic_nrf_spim   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_FULL_NAME   "spi@b000"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_irq   11

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_ORD   73

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_anomaly_58_workaround

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_anomaly_58_workaround   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_anomaly_58_workaround_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_anomaly_58_workaround_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible   {"nordic,nrf-spim"}

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_IDX_0   "nordic,nrf-spim"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_IDX_0_TOKEN   nordic_nrf_spim

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_SPIM

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts   {11 /* 0xb */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_0   11

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_max_frequency

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_max_frequency   8000000

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_max_frequency_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_max_frequency_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_down

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_down   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_down_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_down_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_up

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_up   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_up_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_miso_pull_up_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_overrun_character

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_overrun_character   255

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_overrun_character_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_overrun_character_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg   {45056 /* 0xb000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_0   45056

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_rx_delay_supported

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_rx_delay_supported   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_rx_delay_supported_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_rx_delay_supported_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status   "disabled"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 7)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_spi_b000, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_PATH   "/soc/peripheral@40000000/spi@b000"

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_IDX_0_VAL_ADDRESS   1073786880 /* 0x4000b000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_STATUS_disabled

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_STATUS_disabled   1

◆ DT_N_S_soc_S_peripheral_40000000_S_spi_b000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_spi_b000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_CHILD_IDX   38

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_COMPAT_MATCHES_nordic_nrf_timer

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_COMPAT_MATCHES_nordic_nrf_timer   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_FULL_NAME   "timer@10000"

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_irq   16

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_ORD   75

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_cc_num

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_cc_num   6

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_cc_num_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_cc_num_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible   {"nordic,nrf-timer"}

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_IDX_0   "nordic,nrf-timer"

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_IDX_0_TOKEN   nordic_nrf_timer

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_TIMER

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts   {16 /* 0x10 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_0   16

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_prescaler

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_prescaler   0

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_prescaler_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_prescaler_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg   {65536 /* 0x10000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_0   65536

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_10000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_PATH   "/soc/peripheral@40000000/timer@10000"

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_IDX_0_VAL_ADDRESS   1073807360 /* 0x40010000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_10000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_10000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_CHILD_IDX   39

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_COMPAT_MATCHES_nordic_nrf_timer

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_COMPAT_MATCHES_nordic_nrf_timer   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_FULL_NAME   "timer@11000"

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_irq   17

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_ORD   76

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_cc_num

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_cc_num   6

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_cc_num_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_cc_num_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible   {"nordic,nrf-timer"}

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_IDX_0   "nordic,nrf-timer"

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_IDX_0_TOKEN   nordic_nrf_timer

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_TIMER

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts   {17 /* 0x11 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_0   17

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_prescaler

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_prescaler   0

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_prescaler_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_prescaler_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg   {69632 /* 0x11000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_0   69632

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_11000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_PATH   "/soc/peripheral@40000000/timer@11000"

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_IDX_0_VAL_ADDRESS   1073811456 /* 0x40011000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_11000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_11000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_CHILD_IDX   37

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_COMPAT_MATCHES_nordic_nrf_timer

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_COMPAT_MATCHES_nordic_nrf_timer   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_FULL_NAME   "timer@f000"

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_irq   15

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_ORD   74

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_cc_num

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_cc_num   6

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_cc_num_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_cc_num_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible   {"nordic,nrf-timer"}

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_IDX_0   "nordic,nrf-timer"

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_IDX_0_TOKEN   nordic_nrf_timer

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_TIMER

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts   {15 /* 0xf */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_0   15

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_prescaler

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_prescaler   0

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_prescaler_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_prescaler_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg   {61440 /* 0xf000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_0   61440

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_timer_f000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_PATH   "/soc/peripheral@40000000/timer@f000"

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_IDX_0_VAL_ADDRESS   1073803264 /* 0x4000f000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_timer_f000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_timer_f000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_CHILD_IDX   15

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_COMPAT_MATCHES_nordic_nrf_uarte

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_COMPAT_MATCHES_nordic_nrf_uarte   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_FULL_NAME   "uart@8000"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_irq   8

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_ORD   77

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible   {"nordic,nrf-uarte"}

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_IDX_0   "nordic,nrf-uarte"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_IDX_0_TOKEN   nordic_nrf_uarte

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_UARTE

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_cts_pull_up

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_cts_pull_up   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_cts_pull_up_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_cts_pull_up_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_current_speed

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_current_speed   115200

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_current_speed_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_current_speed_ENUM_IDX   12

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_current_speed_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_current_speed_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_disable_rx

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_disable_rx   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_disable_rx_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_disable_rx_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_hw_flow_control

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_hw_flow_control   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_hw_flow_control_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_hw_flow_control_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts   {8 /* 0x8 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_0   8

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, pinctrl_0, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, pinctrl_0, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_IDX_0   DT_N_S_pin_controller_S_uart0_default

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_IDX_0_PH   DT_N_S_pin_controller_S_uart0_default

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_0_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, pinctrl_1, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, pinctrl_1, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_IDX_0   DT_N_S_pin_controller_S_uart0_sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_IDX_0_PH   DT_N_S_pin_controller_S_uart0_sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_1_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names   {"default", "sleep"}

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, pinctrl_names, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, pinctrl_names, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, pinctrl_names, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, pinctrl_names, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_0   "default"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_0_TOKEN   default

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_0_UPPER_TOKEN   DEFAULT

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_1   "sleep"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_1_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_1_TOKEN   sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_1_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_IDX_1_UPPER_TOKEN   SLEEP

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_pinctrl_names_LEN   2

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg   {32768 /* 0x8000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_0   32768

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_rx_pull_up

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_rx_pull_up   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_rx_pull_up_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_rx_pull_up_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_8000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PATH   "/soc/peripheral@40000000/uart@8000"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_0_TOKEN   default

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_0_UPPER_TOKEN   DEFAULT

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_1_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_1_TOKEN   sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_1_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_IDX_1_UPPER_TOKEN   SLEEP

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_default_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_default_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_default_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_default_IDX   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_default_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_default_IDX_0_PH   DT_N_S_pin_controller_S_uart0_default

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_sleep_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_sleep_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_sleep_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_sleep_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_sleep_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NAME_sleep_IDX_0_PH   DT_N_S_pin_controller_S_uart0_sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_PINCTRL_NUM   2

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_IDX_0_VAL_ADDRESS   1073774592 /* 0x40008000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */ \
31, /* /pin-controller/uart0_default */ \
34, /* /pin-controller/uart0_sleep */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_8000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_8000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_CHILD_IDX   16

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_COMPAT_MATCHES_nordic_nrf_uarte

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_COMPAT_MATCHES_nordic_nrf_uarte   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_FULL_NAME   "uart@9000"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_irq   9

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_ORD   78

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible   {"nordic,nrf-uarte"}

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_IDX_0   "nordic,nrf-uarte"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_IDX_0_TOKEN   nordic_nrf_uarte

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_UARTE

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_cts_pull_up

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_cts_pull_up   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_cts_pull_up_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_cts_pull_up_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_disable_rx

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_disable_rx   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_disable_rx_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_disable_rx_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_hw_flow_control

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_hw_flow_control   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_hw_flow_control_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_hw_flow_control_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts   {9 /* 0x9 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_0   9

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg   {36864 /* 0x9000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_0   36864

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_rx_pull_up

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_rx_pull_up   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_rx_pull_up_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_rx_pull_up_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status   "disabled"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 7)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_9000, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_PATH   "/soc/peripheral@40000000/uart@9000"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_IDX_0_VAL_ADDRESS   1073778688 /* 0x40009000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_STATUS_disabled

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_STATUS_disabled   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_9000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_9000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_CHILD_IDX   17

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_COMPAT_MATCHES_nordic_nrf_uarte

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_COMPAT_MATCHES_nordic_nrf_uarte   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_FULL_NAME   "uart@a000"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_irq   10

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_ORD   79

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible   {"nordic,nrf-uarte"}

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_IDX_0   "nordic,nrf-uarte"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_IDX_0_TOKEN   nordic_nrf_uarte

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_UARTE

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_cts_pull_up

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_cts_pull_up   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_cts_pull_up_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_cts_pull_up_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_disable_rx

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_disable_rx   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_disable_rx_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_disable_rx_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_hw_flow_control

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_hw_flow_control   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_hw_flow_control_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_hw_flow_control_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts   {10 /* 0xa */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_0   10

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, pinctrl_0, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, pinctrl_0, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_IDX_0   DT_N_S_pin_controller_S_uart2_default

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_IDX_0_PH   DT_N_S_pin_controller_S_uart2_default

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_0_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, pinctrl_1, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, pinctrl_1, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_IDX_0   DT_N_S_pin_controller_S_uart2_sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_IDX_0_PH   DT_N_S_pin_controller_S_uart2_sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_1_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names   {"default", "sleep"}

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, pinctrl_names, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, pinctrl_names, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, pinctrl_names, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, pinctrl_names, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_0   "default"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_0_TOKEN   default

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_0_UPPER_TOKEN   DEFAULT

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_1   "sleep"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_1_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_1_TOKEN   sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_1_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_IDX_1_UPPER_TOKEN   SLEEP

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_pinctrl_names_LEN   2

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg   {40960 /* 0xa000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_0   40960

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_rx_pull_up

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_rx_pull_up   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_rx_pull_up_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_rx_pull_up_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status   "disabled"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 7)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_a000, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PATH   "/soc/peripheral@40000000/uart@a000"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_0_TOKEN   default

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_0_UPPER_TOKEN   DEFAULT

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_1_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_1_TOKEN   sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_1_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_IDX_1_UPPER_TOKEN   SLEEP

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_default_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_default_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_default_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_default_IDX   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_default_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_default_IDX_0_PH   DT_N_S_pin_controller_S_uart2_default

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_sleep_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_sleep_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_sleep_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_sleep_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_sleep_IDX_0_PH

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NAME_sleep_IDX_0_PH   DT_N_S_pin_controller_S_uart2_sleep

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_PINCTRL_NUM   2

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_IDX_0_VAL_ADDRESS   1073782784 /* 0x4000a000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */ \
36, /* /pin-controller/uart2_default */ \
38, /* /pin-controller/uart2_sleep */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_STATUS_disabled

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_STATUS_disabled   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_a000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_a000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_CHILD_IDX   18

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_COMPAT_MATCHES_nordic_nrf_uarte

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_COMPAT_MATCHES_nordic_nrf_uarte   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_FULL_NAME   "uart@b000"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_irq   11

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_ORD   80

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible   {"nordic,nrf-uarte"}

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_IDX_0   "nordic,nrf-uarte"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_IDX_0_TOKEN   nordic_nrf_uarte

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_UARTE

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_cts_pull_up

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_cts_pull_up   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_cts_pull_up_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_cts_pull_up_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_disable_rx

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_disable_rx   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_disable_rx_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_disable_rx_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_hw_flow_control

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_hw_flow_control   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_hw_flow_control_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_hw_flow_control_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts   {11 /* 0xb */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_0   11

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg   {45056 /* 0xb000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_0   45056

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_rx_pull_up

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_rx_pull_up   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_rx_pull_up_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_rx_pull_up_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status   "disabled"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 3) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 4) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 5) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 6) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 7)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_uart_b000, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_PATH   "/soc/peripheral@40000000/uart@b000"

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_IDX_0_VAL_ADDRESS   1073786880 /* 0x4000b000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_STATUS_disabled

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_STATUS_disabled   1

◆ DT_N_S_soc_S_peripheral_40000000_S_uart_b000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_uart_b000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_CHILD_IDX   14

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_COMPAT_MATCHES_nordic_nrf_vmc

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_COMPAT_MATCHES_nordic_nrf_vmc   1

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_FULL_NAME   "vmc@3a000"

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_IRQ_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_ORD   81

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible   {"nordic,nrf-vmc"}

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_IDX_0   "nordic,nrf-vmc"

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_IDX_0_TOKEN   nordic_nrf_vmc

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_VMC

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg   {237568 /* 0x3a000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_0   237568

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_PATH   "/soc/peripheral@40000000/vmc@3a000"

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_IDX_0_VAL_ADDRESS   1073979392 /* 0x4003a000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_REQUIRES_ORDS    7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_vmc_3a000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_CHILD_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_CHILD_IDX   36

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_COMPAT_MATCHES_nordic_nrf_wdt

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_COMPAT_MATCHES_nordic_nrf_wdt   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_CHILD

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_RANGE

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FULL_NAME

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_FULL_NAME   "watchdog@18000"

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_EXISTS [1/2]

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_EXISTS [2/2]

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq   24

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_irq_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_IDX_0_VAL_priority_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_IRQ_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_ORD

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_ORD   82

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible   {"nordic,nrf-wdt"}

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, compatible, 0)

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_IDX_0   "nordic,nrf-wdt"

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_IDX_0_TOKEN   nordic_nrf_wdt

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_IDX_0_UPPER_TOKEN   NORDIC_NRF_WDT

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_LEN

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_compatible_LEN   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts   {24 /* 0x18 */, 1 /* 0x1 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, interrupts, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, interrupts, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, interrupts, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, interrupts, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_0   24

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_1   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_interrupts_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg   {98304 /* 0x18000 */, 4096 /* 0x1000 */}

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, reg, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, reg, 1)

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_0

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_0   98304

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_1

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_1   4096

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status   "okay"

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_ENUM_IDX

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_ENUM_IDX   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_ENUM_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_ENUM_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, status, 0) \
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, status, 1) \
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, status, 2) \
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, status, 3)

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000, status, 3, __VA_ARGS__)

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_STRING_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_STRING_TOKEN   okay

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_status_STRING_UPPER_TOKEN   OKAY

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_wakeup_source

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_wakeup_source   0

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_wakeup_source_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_P_wakeup_source_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_PARENT

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_PARENT   DT_N_S_soc_S_peripheral_40000000

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_PATH

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_PATH   "/soc/peripheral@40000000/watchdog@18000"

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_PINCTRL_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_PINCTRL_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_RANGES_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_RANGES_NUM   0

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_IDX_0_VAL_ADDRESS   1073840128 /* 0x40018000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_IDX_0_VAL_SIZE   4096 /* 0x1000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_NUM

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REG_NUM   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REQUIRES_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_REQUIRES_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_S_watchdog_18000_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_S_peripheral_40000000_STATUS_okay

#define DT_N_S_soc_S_peripheral_40000000_STATUS_okay   1

◆ DT_N_S_soc_S_peripheral_40000000_SUPPORTS_ORDS

#define DT_N_S_soc_S_peripheral_40000000_SUPPORTS_ORDS

◆ DT_N_S_soc_S_timer_e000e010_CHILD_IDX

#define DT_N_S_soc_S_timer_e000e010_CHILD_IDX   1

◆ DT_N_S_soc_S_timer_e000e010_COMPAT_MATCHES_arm_armv8m_systick

#define DT_N_S_soc_S_timer_e000e010_COMPAT_MATCHES_arm_armv8m_systick   1

◆ DT_N_S_soc_S_timer_e000e010_EXISTS

#define DT_N_S_soc_S_timer_e000e010_EXISTS   1

◆ DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD

#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD (   fn)

◆ DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_VARGS

#define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_soc_S_timer_e000e010_FOREACH_RANGE

#define DT_N_S_soc_S_timer_e000e010_FOREACH_RANGE (   fn)

◆ DT_N_S_soc_S_timer_e000e010_FULL_NAME

#define DT_N_S_soc_S_timer_e000e010_FULL_NAME   "timer@e000e010"

◆ DT_N_S_soc_S_timer_e000e010_IRQ_NUM

#define DT_N_S_soc_S_timer_e000e010_IRQ_NUM   0

◆ DT_N_S_soc_S_timer_e000e010_ORD

#define DT_N_S_soc_S_timer_e000e010_ORD   46

◆ DT_N_S_soc_S_timer_e000e010_P_compatible

#define DT_N_S_soc_S_timer_e000e010_P_compatible   {"arm,armv8m-systick"}

◆ DT_N_S_soc_S_timer_e000e010_P_compatible_EXISTS

#define DT_N_S_soc_S_timer_e000e010_P_compatible_EXISTS   1

◆ DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_soc_S_timer_e000e010, compatible, 0)

◆ DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__)

◆ DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0

#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0   "arm,armv8m-systick"

◆ DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_EXISTS

#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_TOKEN

#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_TOKEN   arm_armv8m_systick

◆ DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_UPPER_TOKEN

#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_UPPER_TOKEN   ARM_ARMV8M_SYSTICK

◆ DT_N_S_soc_S_timer_e000e010_P_compatible_LEN

#define DT_N_S_soc_S_timer_e000e010_P_compatible_LEN   1

◆ DT_N_S_soc_S_timer_e000e010_P_reg

#define DT_N_S_soc_S_timer_e000e010_P_reg   {3758153744 /* 0xe000e010 */, 16 /* 0x10 */}

◆ DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS

#define DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS   1

◆ DT_N_S_soc_S_timer_e000e010_P_reg_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_timer_e000e010_P_reg_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_timer_e000e010, reg, 0) \
fn(DT_N_S_soc_S_timer_e000e010, reg, 1)

◆ DT_N_S_soc_S_timer_e000e010_P_reg_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_timer_e000e010_P_reg_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_timer_e000e010, reg, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_timer_e000e010, reg, 1, __VA_ARGS__)

◆ DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0

#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0   3758153744

◆ DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0_EXISTS

#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1

#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1   16

◆ DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1_EXISTS

#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1_EXISTS   1

◆ DT_N_S_soc_S_timer_e000e010_P_status

#define DT_N_S_soc_S_timer_e000e010_P_status   "disabled"

◆ DT_N_S_soc_S_timer_e000e010_P_status_ENUM_IDX

#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_IDX   2

◆ DT_N_S_soc_S_timer_e000e010_P_status_ENUM_TOKEN

#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_TOKEN   disabled

◆ DT_N_S_soc_S_timer_e000e010_P_status_ENUM_UPPER_TOKEN

#define DT_N_S_soc_S_timer_e000e010_P_status_ENUM_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_timer_e000e010_P_status_EXISTS

#define DT_N_S_soc_S_timer_e000e010_P_status_EXISTS   1

◆ DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM

#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM (   fn)
Value:
fn(DT_N_S_soc_S_timer_e000e010, status, 0) \
fn(DT_N_S_soc_S_timer_e000e010, status, 1) \
fn(DT_N_S_soc_S_timer_e000e010, status, 2) \
fn(DT_N_S_soc_S_timer_e000e010, status, 3) \
fn(DT_N_S_soc_S_timer_e000e010, status, 4) \
fn(DT_N_S_soc_S_timer_e000e010, status, 5) \
fn(DT_N_S_soc_S_timer_e000e010, status, 6) \
fn(DT_N_S_soc_S_timer_e000e010, status, 7)

◆ DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_soc_S_timer_e000e010_P_status_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)
Value:
fn(DT_N_S_soc_S_timer_e000e010, status, 0, __VA_ARGS__) \
fn(DT_N_S_soc_S_timer_e000e010, status, 1, __VA_ARGS__) \
fn(DT_N_S_soc_S_timer_e000e010, status, 2, __VA_ARGS__) \
fn(DT_N_S_soc_S_timer_e000e010, status, 3, __VA_ARGS__) \
fn(DT_N_S_soc_S_timer_e000e010, status, 4, __VA_ARGS__) \
fn(DT_N_S_soc_S_timer_e000e010, status, 5, __VA_ARGS__) \
fn(DT_N_S_soc_S_timer_e000e010, status, 6, __VA_ARGS__) \
fn(DT_N_S_soc_S_timer_e000e010, status, 7, __VA_ARGS__)

◆ DT_N_S_soc_S_timer_e000e010_P_status_STRING_TOKEN

#define DT_N_S_soc_S_timer_e000e010_P_status_STRING_TOKEN   disabled

◆ DT_N_S_soc_S_timer_e000e010_P_status_STRING_UPPER_TOKEN

#define DT_N_S_soc_S_timer_e000e010_P_status_STRING_UPPER_TOKEN   DISABLED

◆ DT_N_S_soc_S_timer_e000e010_PARENT

#define DT_N_S_soc_S_timer_e000e010_PARENT   DT_N_S_soc

◆ DT_N_S_soc_S_timer_e000e010_PATH

#define DT_N_S_soc_S_timer_e000e010_PATH   "/soc/timer@e000e010"

◆ DT_N_S_soc_S_timer_e000e010_PINCTRL_NUM

#define DT_N_S_soc_S_timer_e000e010_PINCTRL_NUM   0

◆ DT_N_S_soc_S_timer_e000e010_RANGES_NUM

#define DT_N_S_soc_S_timer_e000e010_RANGES_NUM   0

◆ DT_N_S_soc_S_timer_e000e010_REG_IDX_0_EXISTS

#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_EXISTS   1

◆ DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS

#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS   3758153744 /* 0xe000e010 */

◆ DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE

#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE   16 /* 0x10 */

◆ DT_N_S_soc_S_timer_e000e010_REG_NUM

#define DT_N_S_soc_S_timer_e000e010_REG_NUM   1

◆ DT_N_S_soc_S_timer_e000e010_REQUIRES_ORDS

#define DT_N_S_soc_S_timer_e000e010_REQUIRES_ORDS    5, /* /soc */

◆ DT_N_S_soc_S_timer_e000e010_STATUS_disabled

#define DT_N_S_soc_S_timer_e000e010_STATUS_disabled   1

◆ DT_N_S_soc_S_timer_e000e010_SUPPORTS_ORDS

#define DT_N_S_soc_S_timer_e000e010_SUPPORTS_ORDS   /* nothing */

◆ DT_N_S_soc_STATUS_okay

#define DT_N_S_soc_STATUS_okay   1

◆ DT_N_S_soc_SUPPORTS_ORDS

#define DT_N_S_soc_SUPPORTS_ORDS
Value:
6, /* /soc/interrupt-controller@e000e100 */ \
7, /* /soc/peripheral@40000000 */ \
44, /* /soc/gpiote@40031000 */ \
45, /* /soc/memory@20000000 */ \
46, /* /soc/timer@e000e010 */

◆ DT_N_S_zephyr_user_CHILD_IDX

#define DT_N_S_zephyr_user_CHILD_IDX   10

◆ DT_N_S_zephyr_user_EXISTS

#define DT_N_S_zephyr_user_EXISTS   1

◆ DT_N_S_zephyr_user_FOREACH_CHILD

#define DT_N_S_zephyr_user_FOREACH_CHILD (   fn)

◆ DT_N_S_zephyr_user_FOREACH_CHILD_STATUS_OKAY

#define DT_N_S_zephyr_user_FOREACH_CHILD_STATUS_OKAY (   fn)

◆ DT_N_S_zephyr_user_FOREACH_CHILD_STATUS_OKAY_VARGS

#define DT_N_S_zephyr_user_FOREACH_CHILD_STATUS_OKAY_VARGS (   fn,
  ... 
)

◆ DT_N_S_zephyr_user_FOREACH_CHILD_VARGS

#define DT_N_S_zephyr_user_FOREACH_CHILD_VARGS (   fn,
  ... 
)

◆ DT_N_S_zephyr_user_FOREACH_RANGE

#define DT_N_S_zephyr_user_FOREACH_RANGE (   fn)

◆ DT_N_S_zephyr_user_FULL_NAME

#define DT_N_S_zephyr_user_FULL_NAME   "zephyr,user"

◆ DT_N_S_zephyr_user_IRQ_NUM

#define DT_N_S_zephyr_user_IRQ_NUM   0

◆ DT_N_S_zephyr_user_ORD

#define DT_N_S_zephyr_user_ORD   10

◆ DT_N_S_zephyr_user_P_bat_lvl_gpios_EXISTS

#define DT_N_S_zephyr_user_P_bat_lvl_gpios_EXISTS   1

◆ DT_N_S_zephyr_user_P_bat_lvl_gpios_FOREACH_PROP_ELEM

#define DT_N_S_zephyr_user_P_bat_lvl_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_zephyr_user, bat_lvl_gpios, 0)

◆ DT_N_S_zephyr_user_P_bat_lvl_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_zephyr_user_P_bat_lvl_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_zephyr_user, bat_lvl_gpios, 0, __VA_ARGS__)

◆ DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_EXISTS

#define DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_EXISTS   1

◆ DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_PH

#define DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_VAL_flags

#define DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_VAL_flags   0

◆ DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_VAL_pin

#define DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_VAL_pin   12

◆ DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_zephyr_user_P_bat_lvl_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_zephyr_user_P_bat_lvl_gpios_LEN

#define DT_N_S_zephyr_user_P_bat_lvl_gpios_LEN   1

◆ DT_N_S_zephyr_user_P_batchrg_int_gpios_EXISTS

#define DT_N_S_zephyr_user_P_batchrg_int_gpios_EXISTS   1

◆ DT_N_S_zephyr_user_P_batchrg_int_gpios_FOREACH_PROP_ELEM

#define DT_N_S_zephyr_user_P_batchrg_int_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_zephyr_user, batchrg_int_gpios, 0)

◆ DT_N_S_zephyr_user_P_batchrg_int_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_zephyr_user_P_batchrg_int_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_zephyr_user, batchrg_int_gpios, 0, __VA_ARGS__)

◆ DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_EXISTS

#define DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_EXISTS   1

◆ DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_PH

#define DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_VAL_flags

#define DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_VAL_flags   1

◆ DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_VAL_pin

#define DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_VAL_pin   10

◆ DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_zephyr_user_P_batchrg_int_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_zephyr_user_P_batchrg_int_gpios_LEN

#define DT_N_S_zephyr_user_P_batchrg_int_gpios_LEN   1

◆ DT_N_S_zephyr_user_P_batlvl_en_gpios_EXISTS

#define DT_N_S_zephyr_user_P_batlvl_en_gpios_EXISTS   1

◆ DT_N_S_zephyr_user_P_batlvl_en_gpios_FOREACH_PROP_ELEM

#define DT_N_S_zephyr_user_P_batlvl_en_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_zephyr_user, batlvl_en_gpios, 0)

◆ DT_N_S_zephyr_user_P_batlvl_en_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_zephyr_user_P_batlvl_en_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_zephyr_user, batlvl_en_gpios, 0, __VA_ARGS__)

◆ DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_EXISTS

#define DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_EXISTS   1

◆ DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_PH

#define DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_VAL_flags

#define DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_VAL_flags   0

◆ DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_VAL_pin

#define DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_VAL_pin   11

◆ DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_zephyr_user_P_batlvl_en_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_zephyr_user_P_batlvl_en_gpios_LEN

#define DT_N_S_zephyr_user_P_batlvl_en_gpios_LEN   1

◆ DT_N_S_zephyr_user_P_button_max_number

#define DT_N_S_zephyr_user_P_button_max_number   3

◆ DT_N_S_zephyr_user_P_button_max_number_EXISTS

#define DT_N_S_zephyr_user_P_button_max_number_EXISTS   1

◆ DT_N_S_zephyr_user_P_disp_en_gpios_EXISTS

#define DT_N_S_zephyr_user_P_disp_en_gpios_EXISTS   1

◆ DT_N_S_zephyr_user_P_disp_en_gpios_FOREACH_PROP_ELEM

#define DT_N_S_zephyr_user_P_disp_en_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_zephyr_user, disp_en_gpios, 0)

◆ DT_N_S_zephyr_user_P_disp_en_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_zephyr_user_P_disp_en_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_zephyr_user, disp_en_gpios, 0, __VA_ARGS__)

◆ DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_EXISTS

#define DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_EXISTS   1

◆ DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_PH

#define DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_VAL_flags

#define DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_VAL_flags   0

◆ DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_VAL_pin

#define DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_VAL_pin   27

◆ DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_zephyr_user_P_disp_en_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_zephyr_user_P_disp_en_gpios_LEN

#define DT_N_S_zephyr_user_P_disp_en_gpios_LEN   1

◆ DT_N_S_zephyr_user_P_gps_en_gpios_EXISTS

#define DT_N_S_zephyr_user_P_gps_en_gpios_EXISTS   1

◆ DT_N_S_zephyr_user_P_gps_en_gpios_FOREACH_PROP_ELEM

#define DT_N_S_zephyr_user_P_gps_en_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_zephyr_user, gps_en_gpios, 0)

◆ DT_N_S_zephyr_user_P_gps_en_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_zephyr_user_P_gps_en_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_zephyr_user, gps_en_gpios, 0, __VA_ARGS__)

◆ DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_EXISTS

#define DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_EXISTS   1

◆ DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_PH

#define DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_VAL_flags

#define DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_VAL_flags   0

◆ DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_VAL_pin

#define DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_VAL_pin   26

◆ DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_zephyr_user_P_gps_en_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_zephyr_user_P_gps_en_gpios_LEN

#define DT_N_S_zephyr_user_P_gps_en_gpios_LEN   1

◆ DT_N_S_zephyr_user_P_gps_rst_gpios_EXISTS

#define DT_N_S_zephyr_user_P_gps_rst_gpios_EXISTS   1

◆ DT_N_S_zephyr_user_P_gps_rst_gpios_FOREACH_PROP_ELEM

#define DT_N_S_zephyr_user_P_gps_rst_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_zephyr_user, gps_rst_gpios, 0)

◆ DT_N_S_zephyr_user_P_gps_rst_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_zephyr_user_P_gps_rst_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_zephyr_user, gps_rst_gpios, 0, __VA_ARGS__)

◆ DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_EXISTS

#define DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_EXISTS   1

◆ DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_PH

#define DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_VAL_flags

#define DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_VAL_flags   1

◆ DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_VAL_pin

#define DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_VAL_pin   25

◆ DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_zephyr_user_P_gps_rst_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_zephyr_user_P_gps_rst_gpios_LEN

#define DT_N_S_zephyr_user_P_gps_rst_gpios_LEN   1

◆ DT_N_S_zephyr_user_P_io_channels_EXISTS

#define DT_N_S_zephyr_user_P_io_channels_EXISTS   1

◆ DT_N_S_zephyr_user_P_io_channels_FOREACH_PROP_ELEM

#define DT_N_S_zephyr_user_P_io_channels_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_zephyr_user, io_channels, 0)

◆ DT_N_S_zephyr_user_P_io_channels_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_zephyr_user_P_io_channels_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_zephyr_user, io_channels, 0, __VA_ARGS__)

◆ DT_N_S_zephyr_user_P_io_channels_IDX_0_EXISTS

#define DT_N_S_zephyr_user_P_io_channels_IDX_0_EXISTS   1

◆ DT_N_S_zephyr_user_P_io_channels_IDX_0_PH

#define DT_N_S_zephyr_user_P_io_channels_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_adc_e000

◆ DT_N_S_zephyr_user_P_io_channels_IDX_0_VAL_input

#define DT_N_S_zephyr_user_P_io_channels_IDX_0_VAL_input   3

◆ DT_N_S_zephyr_user_P_io_channels_IDX_0_VAL_input_EXISTS

#define DT_N_S_zephyr_user_P_io_channels_IDX_0_VAL_input_EXISTS   1

◆ DT_N_S_zephyr_user_P_io_channels_LEN

#define DT_N_S_zephyr_user_P_io_channels_LEN   1

◆ DT_N_S_zephyr_user_P_led_max_number

#define DT_N_S_zephyr_user_P_led_max_number   3

◆ DT_N_S_zephyr_user_P_led_max_number_EXISTS

#define DT_N_S_zephyr_user_P_led_max_number_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d1com_gpios_EXISTS

#define DT_N_S_zephyr_user_P_motor_d1com_gpios_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d1com_gpios_FOREACH_PROP_ELEM

#define DT_N_S_zephyr_user_P_motor_d1com_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_zephyr_user, motor_d1com_gpios, 0)

◆ DT_N_S_zephyr_user_P_motor_d1com_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_zephyr_user_P_motor_d1com_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_zephyr_user, motor_d1com_gpios, 0, __VA_ARGS__)

◆ DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_EXISTS

#define DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_PH

#define DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_VAL_flags

#define DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_VAL_flags   0

◆ DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_VAL_pin

#define DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_VAL_pin   1

◆ DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_zephyr_user_P_motor_d1com_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d1com_gpios_LEN

#define DT_N_S_zephyr_user_P_motor_d1com_gpios_LEN   1

◆ DT_N_S_zephyr_user_P_motor_d1m1_gpios_EXISTS

#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d1m1_gpios_FOREACH_PROP_ELEM

#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_zephyr_user, motor_d1m1_gpios, 0)

◆ DT_N_S_zephyr_user_P_motor_d1m1_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_zephyr_user, motor_d1m1_gpios, 0, __VA_ARGS__)

◆ DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_EXISTS

#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_PH

#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_VAL_flags

#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_VAL_flags   0

◆ DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_VAL_pin

#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_VAL_pin   0

◆ DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d1m1_gpios_LEN

#define DT_N_S_zephyr_user_P_motor_d1m1_gpios_LEN   1

◆ DT_N_S_zephyr_user_P_motor_d1m2_gpios_EXISTS

#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d1m2_gpios_FOREACH_PROP_ELEM

#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_zephyr_user, motor_d1m2_gpios, 0)

◆ DT_N_S_zephyr_user_P_motor_d1m2_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_zephyr_user, motor_d1m2_gpios, 0, __VA_ARGS__)

◆ DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_EXISTS

#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_PH

#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_VAL_flags

#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_VAL_flags   0

◆ DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_VAL_pin

#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_VAL_pin   2

◆ DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d1m2_gpios_LEN

#define DT_N_S_zephyr_user_P_motor_d1m2_gpios_LEN   1

◆ DT_N_S_zephyr_user_P_motor_d2com_gpios_EXISTS

#define DT_N_S_zephyr_user_P_motor_d2com_gpios_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d2com_gpios_FOREACH_PROP_ELEM

#define DT_N_S_zephyr_user_P_motor_d2com_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_zephyr_user, motor_d2com_gpios, 0)

◆ DT_N_S_zephyr_user_P_motor_d2com_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_zephyr_user_P_motor_d2com_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_zephyr_user, motor_d2com_gpios, 0, __VA_ARGS__)

◆ DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_EXISTS

#define DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_PH

#define DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_VAL_flags

#define DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_VAL_flags   0

◆ DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_VAL_pin

#define DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_VAL_pin   4

◆ DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_zephyr_user_P_motor_d2com_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d2com_gpios_LEN

#define DT_N_S_zephyr_user_P_motor_d2com_gpios_LEN   1

◆ DT_N_S_zephyr_user_P_motor_d2m1_gpios_EXISTS

#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d2m1_gpios_FOREACH_PROP_ELEM

#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_zephyr_user, motor_d2m1_gpios, 0)

◆ DT_N_S_zephyr_user_P_motor_d2m1_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_zephyr_user, motor_d2m1_gpios, 0, __VA_ARGS__)

◆ DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_EXISTS

#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_PH

#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_VAL_flags

#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_VAL_flags   0

◆ DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_VAL_pin

#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_VAL_pin   5

◆ DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d2m1_gpios_LEN

#define DT_N_S_zephyr_user_P_motor_d2m1_gpios_LEN   1

◆ DT_N_S_zephyr_user_P_motor_d2m2_gpios_EXISTS

#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d2m2_gpios_FOREACH_PROP_ELEM

#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_FOREACH_PROP_ELEM (   fn)    fn(DT_N_S_zephyr_user, motor_d2m2_gpios, 0)

◆ DT_N_S_zephyr_user_P_motor_d2m2_gpios_FOREACH_PROP_ELEM_VARGS

#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_FOREACH_PROP_ELEM_VARGS (   fn,
  ... 
)    fn(DT_N_S_zephyr_user, motor_d2m2_gpios, 0, __VA_ARGS__)

◆ DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_EXISTS

#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_PH

#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_PH   DT_N_S_soc_S_peripheral_40000000_S_gpio_842500

◆ DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_VAL_flags

#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_VAL_flags   0

◆ DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_VAL_flags_EXISTS

#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_VAL_flags_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_VAL_pin

#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_VAL_pin   3

◆ DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_VAL_pin_EXISTS

#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_IDX_0_VAL_pin_EXISTS   1

◆ DT_N_S_zephyr_user_P_motor_d2m2_gpios_LEN

#define DT_N_S_zephyr_user_P_motor_d2m2_gpios_LEN   1

◆ DT_N_S_zephyr_user_P_motor_max_number

#define DT_N_S_zephyr_user_P_motor_max_number   3

◆ DT_N_S_zephyr_user_P_motor_max_number_EXISTS

#define DT_N_S_zephyr_user_P_motor_max_number_EXISTS   1

◆ DT_N_S_zephyr_user_PARENT

#define DT_N_S_zephyr_user_PARENT   DT_N

◆ DT_N_S_zephyr_user_PATH

#define DT_N_S_zephyr_user_PATH   "/zephyr,user"

◆ DT_N_S_zephyr_user_PINCTRL_NUM

#define DT_N_S_zephyr_user_PINCTRL_NUM   0

◆ DT_N_S_zephyr_user_RANGES_NUM

#define DT_N_S_zephyr_user_RANGES_NUM   0

◆ DT_N_S_zephyr_user_REG_NUM

#define DT_N_S_zephyr_user_REG_NUM   0

◆ DT_N_S_zephyr_user_REQUIRES_ORDS

#define DT_N_S_zephyr_user_REQUIRES_ORDS
Value:
0, /* / */ \
8, /* /soc/peripheral@40000000/adc@e000 */ \
9, /* /soc/peripheral@40000000/gpio@842500 */

◆ DT_N_S_zephyr_user_STATUS_okay

#define DT_N_S_zephyr_user_STATUS_okay   1

◆ DT_N_S_zephyr_user_SUPPORTS_ORDS

#define DT_N_S_zephyr_user_SUPPORTS_ORDS   /* nothing */

◆ DT_N_STATUS_okay

#define DT_N_STATUS_okay   1

◆ DT_N_SUPPORTS_ORDS

#define DT_N_SUPPORTS_ORDS
Value:
1, /* /aliases */ \
2, /* /chosen */ \
3, /* /cryptocell-sw */ \
4, /* /entropy_bt_hci */ \
5, /* /soc */ \
10, /* /zephyr,user */ \
11, /* /buttons */ \
15, /* /cpus */ \
18, /* /leds */ \
22, /* /pin-controller */ \
40, /* /reserved-memory */
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